Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-12-01
2000-02-01
Chaudhari, Chandra
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438629, 438740, 438970, H01L 2144
Patent
active
060202580
ABSTRACT:
A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
REFERENCES:
patent: 4630357 (1986-12-01), Rogers et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 5882999 (1999-03-01), Anderson et al.
Lur Water
Sun Shih-Wei
Yew Tri-Rung
Chaudhari Chandra
Kilday Lisa A.
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