Method for two-cycle sensing in a two-terminal memory array...

Details Method for two-cycle sensing in a two-terminal memory array... Method for two-cycle sensing in a two-terminal memory array...

2008-03-03

2008-10-14

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S148000, C365S158000

Reexamination Certificate

active

07436723

ABSTRACT:
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

REFERENCES:
patent: 6826080 (2004-11-01), Park et al.
patent: 6870755 (2005-03-01), Rinerson et al.
patent: 7042757 (2006-05-01), Perner
patent: 7372753 (2008-05-01), Rinerson et al.
patent: 7379364 (2008-05-01), Siau et al.
patent: 2008/0007989 (2008-01-01), Kumar et al.
patent: 2008/0144357 (2008-06-01), Siau et al.
U.S. Appl. No. 12/072,813, filed Feb. 28, 2008, Chang Siau et al.

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