Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-15
2006-08-15
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C365S149000, C703S014000
Reexamination Certificate
active
07093208
ABSTRACT:
A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5392221 (1995-02-01), Donath et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 6202192 (2001-03-01), Donath et al.
patent: 6460166 (2002-10-01), Reddy et al.
patent: 6557151 (2003-04-01), Donath et al.
patent: 6574779 (2003-06-01), Allen et al.
patent: 6701289 (2004-03-01), Garnett et al.
patent: 6745371 (2004-06-01), Konstadinidis et al.
patent: 2003/0233628 (2003-12-01), Rana et al.
patent: 2004/0196684 (2004-10-01), Katoh et al.
patent: 2004/0230921 (2004-11-01), Hathaway et al.
patent: 2004/0230929 (2004-11-01), Zhou et al.
patent: 2005/0050497 (2005-03-01), Tetelbaum
patent: 2005/0114814 (2005-05-01), Correale et al.
patent: 2005/0114815 (2005-05-01), Correale et al.
G. A. Northrop et al., A Semi-Custom Design Flow in High-Performance Microprocessor Design, Proc. 2001 Design Automation Conference, Las Vegas, Nevada, pp. 426-431, Jun. 2001.
A. R. Conn et al., Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation, Proc. 1999 Design Automation Conference, New Orleans, La., pp. 425-429, Jun. 1999.
W. Liqiong et al., Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits, Proc. 1998 Design Automation Conference, San Fransisco, Ca., pp. 489-494, Jun. 1998.
M. Ketkar et al., Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment, Prof. International Conference on Computer-Aided Design (ICCAD), San Jose, Ca., pp. 375-378, Nov. 2002.
Cho Ee K.
Hathaway David J.
Hsu Mei-Ting
Lange Lawrence K.
Northrop Gregory A.
Augspurger Lynn L.
International Business Machines - Corporation
Lam Nelson
Thompson A. M.
LandOfFree
Method for tuning a digital design for synthesized random... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for tuning a digital design for synthesized random..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for tuning a digital design for synthesized random... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3700662