Method for trench isolation of semiconductor devices

Details Method for trench isolation of semiconductor devices Method for trench isolation of semiconductor devices

1999-01-11

2001-05-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000, C438S431000

Reexamination Certificate

active

06228741

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and especially to producing a planar surface after shallow trench isolation without chemical-mechanical polishing.
Background: Shallow Trench Isolation and Chemical Mechanical Polishing
Shallow Trench Isolation (STI) proceeds by etching a trench in the silicon wafer and backfilling the trench with a suitable insulator material. Since the backfill process deposits the insulator on the active areas as well as in the trench, the excess insulator material must be removed in a manner that results in a flat surface that is level with the active area surface.
Current STI methods use chemical mechanical polishing (CMP) to remove the excess insulator material and level it to the active area surface. The CMP process suffers from non-uniformities arising from varying polish rates across the wafer and across the die (due to differences in circuitry density).
Current STI methods attempt to compensate for the CMP non-uniformities by adding extra, non-functional moat to wide field oxide areas. This is only partly successful, because there are some areas that cannot maintain proper circuit operation in the presence of additional moat. Other compensation methods add trench etch patterns to the edge of the wafer to attempt to reduce the wafer level non-uniformity.
Innovative Structures and Methods
It is herein disclosed that the CMP process can be eliminated after shallow trench formation by a careful sequence of deposition and etch, both of which are more uniform processes than CMP. The trench is patterned and etched according to known methods, using a nitride mask. The trench is then filled using a process which simultaneously deposits and etches, such as high density plasma (HDP), producing planar surfaces over the trench and active areas and a sloped surface between the two planes. The edge of the nitride is not covered during the deposition and a short etch of the oxide further exposes the nitride corner without appreciably removing any oxide. A cap nitride is then deposited over the entire surface and, together with the original nitride mask, will seal the trench from contact with the surface. The cap nitride is patterned, using any of various methods, including, but not limited to, photolithography, polymer spin-on and etchback, and oxide spin-on and etchback, to expose the cap nitride over the active areas only. The cap nitride is etched, selective to the oxide, to leave the cap only over the trenches. This exposes the oxide over the active area, which may be removed with an etch which is selective to the nitride. Once the oxide is removed, both the cap nitride and the original mask nitride are removed, leaving planar active area surfaces and only a small thickness of trench oxide above the surface. Processing then proceeds with known methods.
Advantages of the disclosed methods and structures include:
produces a uniform surface across die and wafer;
eliminates need for non-functional moat;
eliminates need for extra trench etch patterns;
uses standard processes;
eliminates need for chemical-mechanical polishing (CMP); and
reduces cost of fabrication.


REFERENCES:
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patent: 5786263 (1998-07-01), Perera
patent: 5976947 (1999-11-01), Reinberg
patent: 5976951 (1999-11-01), Huang et al.
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patent: 60-53045 (1983-09-01), None
patent: 60-64445 (1983-09-01), None
Author unknown. IBM Corp. “Selective planarization process and structures”. IBM Technical Disclosure Bulletin, Sep. 1984, US. vol. 27, No. 4b, pp. 2560-2563, XP-002110920.

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