Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2008-12-15
2011-11-15
Maldonado, Julio J (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S476000, C438S703000, C257SE21224, C257SE21054, C257SE21603, C257SE21605, C257SE21699
Reexamination Certificate
active
08058174
ABSTRACT:
A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level. The skin impurity level is average impurity level from 0 nm to 100 nm of depth into the outer surface portion, the bulk impurity level is measured at a depth of at least 3 microns into the outer surface portion, and the skin impurity level is not greater than 80% of the bulk impurity level.
REFERENCES:
patent: 1900053 (1933-03-01), Glidden
patent: 2233434 (1941-03-01), Smith
patent: 3219182 (1965-11-01), Cornwell, Jr.
patent: 3951587 (1976-04-01), Alliegro et al.
patent: 4836965 (1989-06-01), Hayashi et al.
patent: 4859385 (1989-08-01), Tanaka et al.
patent: 4889686 (1989-12-01), Singh et al.
patent: 4900531 (1990-02-01), Levin
patent: 4944904 (1990-07-01), Singh et al.
patent: 4978567 (1990-12-01), Miller
patent: 4981822 (1991-01-01), Singh et al.
patent: 4982068 (1991-01-01), Pollock et al.
patent: 4998879 (1991-03-01), Foster et al.
patent: 5021367 (1991-06-01), Singh et al.
patent: 5043303 (1991-08-01), Singh et al.
patent: 5079039 (1992-01-01), Heraud et al.
patent: 5194330 (1993-03-01), Vandenbulcke et al.
patent: 5238619 (1993-08-01), McGuigan et al.
patent: 5494439 (1996-02-01), Goldstein et al.
patent: 5494524 (1996-02-01), Inaba et al.
patent: 5509555 (1996-04-01), Chiang et al.
patent: 5514439 (1996-05-01), Sibley
patent: 5538230 (1996-07-01), Sibley
patent: 5589116 (1996-12-01), Kojima et al.
patent: 5628938 (1997-05-01), Sangeeta et al.
patent: 5738908 (1998-04-01), Rey et al.
patent: 5752609 (1998-05-01), Kato et al.
patent: 5770324 (1998-06-01), Holmes et al.
patent: 5834387 (1998-11-01), Divakar et al.
patent: 5846611 (1998-12-01), Christin
patent: 5897311 (1999-04-01), Nishi
patent: 5904892 (1999-05-01), Holmes
patent: 5942454 (1999-08-01), Nakayama et al.
patent: 6024898 (2000-02-01), Steibel et al.
patent: 6062853 (2000-05-01), Shimazu et al.
patent: 6066572 (2000-05-01), Lu et al.
patent: 6093644 (2000-07-01), Inaba et al.
patent: 6099645 (2000-08-01), Easley et al.
patent: 6162543 (2000-12-01), Dubots et al.
patent: 6277194 (2001-08-01), Thilderkvist et al.
patent: 6296716 (2001-10-01), Haerle et al.
patent: 6357604 (2002-03-01), Wingo
patent: 6379575 (2002-04-01), Yin et al.
patent: 6383298 (2002-05-01), Ross et al.
patent: 6395203 (2002-05-01), Brun
patent: 6401941 (2002-06-01), Maumus
patent: 6403155 (2002-06-01), Dubots et al.
patent: 6410088 (2002-06-01), Robin-Brosse et al.
patent: 6455160 (2002-09-01), Hiraoka et al.
patent: 6488497 (2002-12-01), Buckley et al.
patent: 6536608 (2003-03-01), Buckley
patent: 6565667 (2003-05-01), Haerle et al.
patent: 6617540 (2003-09-01), Zehavi
patent: 6670294 (2003-12-01), Kobayashi
patent: 6723437 (2004-04-01), Haerle et al.
patent: 6776289 (2004-08-01), Nyseth
patent: 6811040 (2004-11-01), Payne et al.
patent: 6825123 (2004-11-01), Haerle et al.
patent: 6874638 (2005-04-01), Iijima et al.
patent: 6881262 (2005-04-01), Haerle et al.
patent: 6890861 (2005-05-01), Bosch
patent: 7053411 (2006-05-01), Haerle et al.
patent: 7501370 (2009-03-01), Narendar et al.
patent: 2002/0113027 (2002-08-01), Minami et al.
patent: 2002/0130061 (2002-09-01), Hengst
patent: 2002/0168867 (2002-11-01), Haerle et al.
patent: 2003/0198749 (2003-10-01), Kumar et al.
patent: 2003/0233977 (2003-12-01), Narendar et al.
patent: 2004/0129203 (2004-07-01), Zehavi et al.
patent: 2004/0208815 (2004-10-01), Haerle et al.
patent: 2004/0235231 (2004-11-01), Narendar et al.
patent: 2466183 (2003-05-01), None
patent: 1662471 (2006-08-01), None
patent: 19749462 (1999-03-01), None
patent: 0582444 (1994-02-01), None
patent: 0915070 (1999-05-01), None
patent: 0924750 (1999-06-01), None
patent: 1061042 (2000-12-01), None
patent: 1072570 (2001-01-01), None
patent: 1094129 (2001-04-01), None
patent: 1184355 (2002-03-01), None
patent: 1219578 (2002-07-01), None
patent: 893041 (1962-04-01), None
patent: 1394106 (1975-05-01), None
patent: 2130192 (1984-05-01), None
patent: 7328360 (1995-12-01), None
patent: 10197837 (1998-07-01), None
patent: 10228974 (1998-08-01), None
patent: 10253259 (1998-09-01), None
patent: 11209115 (1999-08-01), None
patent: 2000044223 (2000-02-01), None
patent: 2002338366 (2002-11-01), None
patent: 00/18702 (2000-04-01), None
patent: 02/09161 (2002-01-01), None
patent: 04/000756 (2003-12-01), None
patent: 2004/093150 (2004-10-01), None
patent: 2005/068395 (2005-07-01), None
B. Leroy et al., “Warpage of Silicon Wafers,” Journal Electrochemical Society, vol. 127, No. 4, Apr. 1980, pp. 961-970.
Daihan Scientific “Daihan” Alumina Crucible, B-from, General—type, Copyright 2004, printed from http://www.daihan-sci.com/catalogs—detail.asp?itemgrnum=1499&productgrname=Crucibles&productgrn . . . , Printed on Aug. 11, 2006.
Ghandi, “VLSI Fabrication Principles, Silicon and Gallium Aresnide”, 1983, John Wiley and Sons, pp. 517-520.
H. Rauh, “Atlas for Characterization of Defects in Silicon,” Wacker Siltronic AG, Burghausen, Germany, pp. 1-64, 2004.
Hyper-Therm High-Temperature Composites, Inc. “Ceramic-Matrix Composites”, Feb. 27, 2003, Huntington Beach, CA, USA, Copyright 2000, Printed from http://www.htcomposites.com/fiber—reinforced—ceramics—technology.htm, Printed on Aug. 11, 2006.
Machinery Handbook, 24th Edition, Industrial Press, Copyright 1992, pp. 1598-1603.
M. Schrems et al., “Simulation of Temperature Distributions During Fast Thermal Processing,” Journal Electrochemical Society, Semiconductor Silicon, 1994, pp. 1050-1059.
Nilson et al., “Scaling wafer stresses and thermal processes to large wafers,” Thin Solid Films 315, 1998, pp. 286-293.
R. F. Buckley et al., “Design and Analysis of a Semiconductor Wafer Processing System for 30 mm Wafers,” MS Thesis—Worcester Polytechnic Institute, Dec. 29, 1999, pp. 1-62.
Shigley et al., “Mechanical Engineering Design,” McGraw Hill, copyright 1989, p. 62, p. 159.
Van Zant, “Microchip Fabrication: A Practical Guide to Semiconductor Processing,” McGraw Hill, Fourth Edition, 1990, chapters 3-7.
Wolf, et al., “Silicon Processing for the VLSI Era, vol. 1”, Process Technology, 1986 Lattice Press, pp. 215-216.
U.S. Appl. No. 10/176,202, filed Jun. 2, 2002, Inventors: Yeshwanth Narendar et al.
U.S. Appl. No. 10/752,434, filed Jan. 6, 2004, Inventors: Yeshwanth Narendar et al.
U.S. Appl. No. 10/328,251, filed Dec. 23, 2002, Inventors: Andrew G. Haerle et al.
U.S. Appl. No. 10/414,563, filed Apr. 15, 2003, Inventors: Andrew G. Haerle et al.
U.S. Appl. No. 10/828,680, filed Apr. 21, 2004, Inventors: Andrew G. Haerle et al.
U.S. Appl. No. 10/824,329, filed Apr. 14, 2004, Inventors: Yeshwanth Narendar et al.
U.S. Appl. No. 12/567,969, filed Sep. 28, 2009, Inventors: Yeshwanth Narendar et al.
Buckley Richard F.
Narendar Yeshwanth
CoorsTek, Inc.
Fonda David
Maldonado Julio J
LandOfFree
Method for treating semiconductor processing components and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for treating semiconductor processing components and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for treating semiconductor processing components and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4258034