Method for translating conditional expressions from a...

Details Method for translating conditional expressions from a... Method for translating conditional expressions from a...

2000-06-01

2003-05-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06564354

ABSTRACT:

FIELD OF THE INVENTION
The presented invention relates generally to the use of hardware description languages to specify circuit logic design in a format that is acceptable to logic synthesis tools, and, more particularly, to a method for translating non-Verilog HDL containing conditional expressions to Verilog HDL format and syntax.
BACKGROUND OF THE INVENTION
The soundness of logic design of hardware such as complex central processor units (CPUs) must be tested prior to actually manufacturing the hardware. Logic design may be specified in the form of Boolean equations or a hardware description language (HDL) description in a language such as Verilog HDL, an IEEE standard hardware description language (IEEE Std 1364-1995). A routine can be written in an HDL such as Verilog HDL and then be converted into a logic gate circuit using a logical synthesis tool, such as Synopsys Design Compiler™, operating on a general-purpose computer. In this manner, the logic design can be proven out.
Verilog HDL, as an accepted standard, is a language accepted as an input format by many design tools available on the market today. A concern arises, therefore, when a hardware description language other than Verilog HDL is used, generically referred to as a non-Verilog HDL, since third party design tools that will accept Verilog HDL may not readily accept another HDL. Since it is desirable to increase design productivity and to thus shorten the design cycle of CPUs and other relevant hardware, it is important to leverage existing and advanced tools even if they do not accept the non-Verilog HDL. This requires that the non-Verilog HDL be translated into Verilog HDL so that it can be readily used with available tools. An important aspect of the translation into Verilog HDL is that the translation be logically correct; additionally, certain inherent semantics of the code must be preserved. Logic synthesis tools such as the Synopsys Design Compiler™ must be able to produce optimal results from the translated code.
A difficulty is encountered in the translation process when certain conditional expressions that are frequently used in the non-Verilog HDL are missing in Verilog HDL syntax and thus not recognized by the Verilog HDL. These conditional expressions may be broken into three types: IF expressions, CASE expressions, and COND expressions. An IF expression provides a choice between several expressions. The format of an IF expression is:
IF ifcond THEN exp1 ELSE exp2
A CASE expression returns the value of one expression out of N expressions, depending upon the value of a controlling expression. The format of a CASE expression is:
CASE caseexpr OF BEGIN
[c
1
] exp1;
[c
2
] exp2;
.
.
.
[cN] expN;
[ ] expN+1;
END;
A COND expression returns the value of one expression out of N expressions, depending on the value of the controlling expressions. The format of a COND expression is as follows:
COND BEGIN
[sel_exp1] exp1;
[sel_exp2] exp2;
.
.
.
[ ] expN+1;
END;
These types of expressions (IF/CASE/COND) will be generically referred to as “ICC expressions” hereafter.
The approaches to translating the various types of ICC expressions into Verilog HDL each have problems. First, a possible solution is the use of a nested conditional operator “?:” in the translated expression to implement the logic of the ICC expression that was translated. Consider the following examples. An IF expression of a:=IF b THEN c ELSE d; can be translated to a=b ? c: d; and a CASE expression of:
a:=CASE caseExp OF BEGIN
[′00] b;
[′01] c;
[′10] d;
[′11] e;
[ ] RETAIN;
END;
can be translated to
a=(caseExp==2′b00) ? b
:(caseExp==2′b01) ? c
:(caseExp==2′b10) ? d
:(caseExp==2′b11) ? e
a;
A COND expression is translated in a similar fashion to the CASE expression.
In the above translations of the IF and CASE expressions into Verilog, note the occurrence of the “?:” nested conditional operator. This approach to translating is simple and the generated Verilog HDL is clean and easy to read. Unfortunately, however, the performance of the generated Verilog code is very bad. What could be done with a single multiplexer in the pre-translated code is instead interpreted by logic synthesis tools as a multi-level chain of multiplexers in the translated code. This leads to very poor synthesis results as will be later described.
Second, ICC expressions of non-Verilog HDL code can be translated to Verilog “IF”, “CASE” statements as shown below. Consider the same IF and COND expressions above. For the IF expression of a:=IF b THEN c ELSE d; the translation would be:
always @(b or c or d)
if(b)
a=c;
else
a=d;
The above CASE expression of:
a:=CASE caseExp OF BEGIN
[′00] b;
[′01] c;
[′10] d;
[′11] e;
[ ] RETAIN;
END;
can be translated to
always @(caseExp or b or c or d or e)
begin
case (caseExp)
2′b00: a=b;
2′b01: a=c;
2′b10: a=d;
2′b11: a=e;
default: a=a;
endcase
This second approach overcomes the shortcoming of the first approach since synthesis tools can recognize that a CASE statement can be interpreted as a single multiplexer rather than a multiple-level chain of multiplexers. A high quality implementation can thus be generated from the translated Verilog code using this approach.
This solution, however, has a severe limitation because it only works for non-nested ICC(IF/CASE/COND) expressions. But since ICC expressions may occur anywhere within another expression and thus be nested, this approach is limited in its usefulness. Consider, for instance, the following expression containing a nested IF expression that cannot be readily translated using this second approach:
a:=IF ( IF b THEN ′010 ELSE ′111)
THEN d
ELSE e;
Also, consider this additional example of an expression containing a nested ICC expression:
a:=(IF(b) THEN c ELSE d) XOR COND BEGIN
[sel_exp1] e;
[sel_exp2] f;
[sel_exp3] IF (g) THEN h ELSE i;
[ ] j;
END;
In both of these examples, there is no way to readily translate the code to Verilog IF/CASE statements and so the first approach, with its poor synthesis performance, must be used for code containing nested ICC expressions.
The properties associated with each of these two prior art approaches is best illustrated by example. Consider that the following is an example of a software module written in a non-Verilog HDL; note that the software module usually is written for the cell or block hardware level:
fub mux;
begin “mux”
interface(
input node in
1
[
3
:
0
];
input node in
2
[
3
:
0
];
input node in
3
[
3
:
0
];
input node in
4
[
3
:
0
];
input node in
5
[
3
:
0
];
input node in
6
[
3
:
0
];
input node in
7
[
3
:
01
];
input node in
8
[
3
:
0
];
input node sel[
2
:
01
];
output node out[
3
:
0
];
);
structural main;
begin “muxd
4
v main”
out:=
case sel of
begin
[′000] in
1
;
[′001] in
2
;
[′010] in
3
;
[′011] in
4
;
[′100] in
5
;
[′101] in
6
;
[′110] in
7
;
[′111] in
8
;
end;
end “mux main”;
end “mux”;
If this software module is translated to Verilog HDL with the first approach using the “?:” Verilog conditional operator, the result would be as follows:
module mux(in
1
,in
2
,in
3
,in
4
,in
5
,in
6
,in
7
,in
8
,sel,out);
input [
3
:
0
] in
1
;
input [
3
:
0
] in
2
;
input [
3
:
0
] in
3
;
input [
3
:
0
] in
4
;
Input [
3
:
0
] in
5
;
input [
3
:
0
] in
6
;
input [
3
:
0
] in
7
;
input [
3
:
0
&rs

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