Method for translating conditional expressions from a...

Details Method for translating conditional expressions from a... Method for translating conditional expressions from a...

2000-07-25

2003-09-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C717S141000, C717S159000

Reexamination Certificate

active

06625798

ABSTRACT:

FIELD OF THE INVENTION
The presented invention relates generally to the use of hardware description languages to specify circuit logic design in a format that is acceptable to logic synthesis tools, and, more particularly, to a method for translating non-Verilog HDL containing conditional expressions to Verilog HDL format and syntax.
BACKGROUND OF THE INVENTION
The soundness of logic design of hardware such as complex central processor units (CPUs) must be tested prior to actually manufacturing the hardware. Logic design may be specified in the form of Boolean equations or a hardware description language (HDL) description in a language such as Verilog HDL, an IEEE standard hardware description language (IEEE Std 1364-1995). A routine can be written in an HDL such as Verilog HDL and then be converted into a logic gate circuit using a logical synthesis tool, such as Synopsys Design Compiler™, operating on a general-purpose computer. In this manner, the logic design can be realized.
Verilog HDL, as an accepted standard, is a language accepted as an input format by many design tools available on the market today. A concern arises, therefore, when a hardware description language other than Verilog HDL is used, generically referred to as a non-Verilog HDL, since third party design tools that will accept Verilog HDL may not readily accept another HDL. Since it is desirable to increase design productivity and to thus shorten the design cycle of CPUs and other relevant hardware, it is important to leverage existing and advanced tools even if they do not accept the non-Verilog HDL. This requires that the non-Verilog HDL be translated into Verilog HDL so that it can be readily used with available tools. An important aspect of the translation into Verilog HDL is that the translation be logically correct; additionally, certain inherent semantics of the code must be preserved. Logic synthesis tools such as the Synopsys Design Compiler™ must be able to produce optimal results from the translated code.
A major concern with the translation process is encountered when certain syntax features of the non-Verilog HDL are not part of the Verilog HDL target language. Multiple-bit IF conditional expressions, for instance, are missing from the Verilog HDL and thus translating them from the non-Verilog HDL to Verilog HDL presents a problem. This means that a multi-bit IF expression in a non-Verilog HDL cannot be directly translated into Verilog HDL syntax without generating incorrect logic.
An IF expression provides a choice between several expressions. The format of an IF expression is:
IF ifcond THEN exp
1
ELSE exp
2
ifcond may be an expression that returns a 1-bit Boolean value, which is supported by Verilog HDL, or it may be a multiple-bit NODE expression that has no Verilog HDL equivalent.
For an IF expression in the multi-bit form, ifcond represents a multiple bit expression that describes the respective single-bit values for a vector of signals. In the above example, the expressions exp
1
and exp
2
must be the same width as ifcond, where the width, in bits, defines the number of signals being represented by the IF expression. For each bit indicated in ifcond, a bit check is made. If the bit being checked, referred to here as bit i, is equal to a Boolean logic “1,” then bit i in exp
1
is chosen for assignment. Otherwise, bit i from exp
2
is chosen for assignment.
Verilog HDL syntax does not support IF expressions. The only Verilog HDL feature similar to an IF expression is the IF statement and in most cases, the IF expression can be translated to a Verilog HDL IF statement without loss of accuracy. For example, the following non-Verilog code:
a:=IF b THEN c ELSE d;
can be translated to:
always@(b or c or d)
if(b)
a=c;
else
a=d;
Verilog HDL does not have a definition of ifcond that is consistent with how ifcond may be defined in a non-Verilog HDL. In Verilog HDL, ifcond will always return a Boolean value, even if it is a multiple-bit expression. This means that a non-Verilog HDL multi-bit IF expression cannot be directly translated into a simple Verilog IF statement; to do so, would render an incorrect translation that would cause incorrect logic to be generated. Consider the following code that contains an IF expression, IF (a) THEN sigc ELSE siga;:
FUB test;
BEGIN “test”
INTERFACE(INPUT NODE siga[
8
];
INPUT NODE sigc[
8
];
INPUT NODE A[
8
];
OUTPUT NODE out[
8
];);
STRUCTURAL MAIN;
BEGIN
Out:=IF (a) THEN sigc ELSE siga;
END;
END;
Directly translating the IF expression contained in this code to a conditional Verilog HDL statement (IF-ELSE statement), will result in the following code:
module test
1
(siga,sigc,out,a);
input [
7
:
0
] siga;
input [
7
:
0
] sigc;
input [
7
:
0
] a;
output [
7
:
0
] out;
/* “tc
19
main” */
reg [
7
:
0
] out;
always @ (sigc or siga or a)
begin
if(a)
out=sigc;
else
out=siga;
end
endmodule
In the translation, the eight-bit IF expression in the original non-Verilog HDL is not reflected in the simple IF statement that is produced by the direct translation.
FIG. 1
shows the results from performing synthesis using this incorrect translation and it is clear that the intended functionality of the multi-bit IF expression has been lost in the translation process from the original non-Verilog HDL to Verilog. More importantly, this simple and direct, but incorrect, translation does not provide any error, warning, or other indication that the translation is incorrect. The synthesis result may be generated from the code by a logic synthesis tool such as the Synopsys Design Compiler™.
A possible solution to this problem is to translate each multi-bit IF expression into N if-else statements in Verilog HDL, where N represents the number of bits within the ifcond. Using this approach, for example, the above code could be translated as follows:
module tc
1
(siga,sigc,out, a);
input [
7
:
0
] siga;
input [
7
:
0
] sigc;
input [
7
:
0
] a;
output [
7
:
0
] out;
reg [
7
:
0
] out;
always @(sigc or siga or a)
begin
if(a[
0
])
out[
0
]=sigc[
0
];
else
out [
0
]=siga[
0
];
if(a[
1
])
out[
1
] sigc[
1
];
else
out[
1
]=siga[
1
];
if(a[
2
])
out[
2
]=sigc[
2
];
else
out[
2
]=siga[
2
];
if(a[
3
])
out[
3
]=sigc[
3
];
else
out[
3
]=siga[
3
];
if(a[
4
])
out[
4
]=sigc[
4
];
else
out[
4
]=siga[
4
];
if(a [
5
])
out[
5
]=sigc[
5
];
else
out[
5
]=siga[
5
];
if(a[
6
])
out[
6
]=sigc[
6
];
else
out[
6
]=siga[
6
];
if(a[
7
])
out[
7
]=sigc[
7
];
else
out[
7
]=siga[
7
];
end
endmodule
FIGS. 2 and 3
(optimized) illustrate the synthesis result that is generated from the above code by a logic synthesis tool such as the Synopsys Design Compiler.™ As shown in these figures, the straightforward solution translates the single assign statement, which contains the multi-bit IF expression, into eight different Verilog IF statements, all for the same operation. The implication of this approach is a significant increase in the complexity associated with translation. Consider, for example, a situation in which either exp
1
or exp
2
within the IF expression are also a multi-bit IF expression, resulting in nested multi-bit IF expressions. Likewise, either exp
1
or exp
2
could also be multi-bit subfield expressions (or expressions within a field of an IF expression), which would further complicate the necessary translation, making it impossible to really resolve. At a minimum, the translated code would be diff

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