Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-11-20
1999-05-11
Donaghue, Larry D.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711120, 395376, G06F12/00
Patent
active
059039108
ABSTRACT:
A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer. A signal is asserted by the first cache to inform the second cache of the need to perform a victim line copyback. Requests from the execute stage of the instruction processing pipeline are stalled to allow the copyback to occur.
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Johnson William M.
Pflum Marty L.
Tran Thang M.
Witt David B.
Advanced Micro Devices , Inc.
Davis Jr. Walter D.
Donaghue Larry D.
Kivlin B. Noel
Merkel Lawrence J.
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