Method for transferring data associated with a read/write...

Details Method for transferring data associated with a read/write... Method for transferring data associated with a read/write...

1997-12-09

2001-06-19

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C711S167000, C711S004000, C711S168000, C711S169000, C711S157000, C711S170000, C711S217000, C711S220000, C710S060000, C710S061000, C710S033000, C710S052000

Reexamination Certificate

active

06249827

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. #_
1
illustrates a memory circuit #_
100
according to the prior art. The memory circuit #_
100
includes a controller #_
110
and DRAMs #_
120
a, #_
120
b, . . . , #_
120
&agr;. The controller #_
110
and the DRAMs #_
120
are communicatively connected by means of a data bus #_
130
and a clock bus #_
140
. A resistor R
t
#_
150
ties each of the busses #_
130
and #_
140
to a voltage source #_
160
at a threshold voltage V
t
.
The circuit components #_
110
, #_
120
each includes a D latch #_
1
A
0
, a receive clock buffer #_
170
and transmit clock and data drivers #_
180
and #_
190
. The data input of the D latch #_
1
A
0
is coupled to the data bus #_
130
. The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_
230
.
Digital logic implements each of the drivers #_
170
, #_
180
and #_
190
. The input-output function of the drivers is essentially a threshold function.
The data bus #_
130
is a read/write bidirectional link. The circuit #_
100
uses the bus #_
130
to transfer write data from the controller #_
110
to a DRAM #_
120
and to transfer read data from a DRAM #_
120
to the controller #_
110
.
The operation of the data bus #_
130
occurs at a sufficiently high speed to require timing information with both read and write data. The data clock is used to latch the data.
FIG. #_
2
illustrates example clock and data signals #_
210
and #_
220
, asserted on the clock and data busses #_
140
and #_
130
, as well as an example internal clock signal #_
230
as received in a receiving device. As FIG. #_
2
illustrates, the data and clock busses #_
130
and #_
140
terminate to the midpoint threshold reference voltage V
t
.
When the memory circuit #_
100
passes control among the controller #_
110
and the DRAMs #_
120
, the device A relinquishing control disables its data output and data clock drivers #_
180
and #_
190
. The disabling allows the busses #_
130
, #_
140
to return to a high impedance state. The device B taking control begins driving the data and clock busses #_
130
, #_
140
.
A problem occurs, however, in the device C (which may be the same as A) receiving the data: During the (brief) period of transition of control from one circuit #_
100
component #_
110
, #_
120
to another, the clock input #_
210
through the buffer #_
170
can be at a high impedance state at or near the threshold voltage V
t
. The receiving device C may receive spurious clock edges #_
250
, corrupting the data received.
FIG. #_
3
illustrates another memory circuit #_
300
according to the prior art. The memory circuit #_
300
includes a controller #_
310
and DRAMs #_
320
a, #_
320
b, . . . , #_
320
&bgr;. The controller #_
310
and the DRAMs #_
320
are communicatively connected by the data bus #_
130
and the clock bus #_
140
tied by resistors R
t
#_
150
to the voltage source #_
160
.
The data bus #_
130
is a read/write bidirectional link. The circuit #_
300
transfers write data from the controller #_
310
to a DRAM #_
320
on the bus #_
130
and transfers read data from a DRAM #_
320
to the controller #_
310
on the bus #_
130
.
Each of the circuit #_
300
components #_
310
, #_
320
includes a D latch #_
1
A
0
, a receive clock buffer #_
340
and transmit clock and data drivers #_
180
and #_
190
. The data input of the D latch #_
1
A
0
is coupled to the data bus #_
130
. The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_
340
.
The clock input buffers #_
340
have input-output functions with hysteresis. As the graph of FIG. #_
6
shows, the output of a buffer #_
340
depends on both the input voltage and the history of the input to the buffer.
When the memory circuit #_
100
passes control among the controller #_
110
and the DRAMs #_
120
, the device relinquishing control disables its data output drivers #_
180
and data clock drivers #_
190
. The disabling allows the busses #_
130
, #_
140
to return to a high impedance state. The device taking control begins driving the data and clock busses #_
130
, #_
140
.
FIG. #_
6
illustrates the example data signal #_
210
asserted on the data bus #_
130
of the circuit #_
300
and an example internal clock signal #_
350
as received in a receiving device through a buffer #_
340
, given the clock signal #_
210
. As FIG. #_
6
shows, the hysteretic buffer #_
340
defeats the spurious clock edges #_
250
.
The buffers #_
340
, however, also defeat the predetermined matched delay of the data and clock paths using the D latch #_
1
A
0
and the clock buffer #_
170
. The mismatch between clock and data also depends on the input slew rate.
Further, the hysteretic buffer #_
340
has less input drive differential for equal amplitude signal. This reduces the speed potential of such a memory circuit.
According, there is a need for a memory circuit that, in operation, does not generate spurious clock edges as a clock signal approaches the high impedance state. One objective of the invention is such a memory circuit.
These and other objectives of the invention will be readily apparent to one of ordinary skill in the art on the reading of the background above and the description below.
SUMMARY OF THE INVENTION
Herein is disclosed a memory circuit with glitchless transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads.
In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.


REFERENCES:
patent: 3735277 (1973-05-01), Wanlass
patent: 3883853 (1975-05-01), O'Brien et al.
patent: 4366538 (1982-12-01), Johnson et al.
patent: 4371928 (1983-02-01), Barlow et al.
patent: 4503494 (1985-03-01), Hamilton et al.
patent: 5058051 (1991-10-01), Brooks
patent: 5394541 (1995-02-01), Chesley et al.
patent: 5428804 (1995-06-01), Davies
patent: 5696730 (1997-12-01), Slezak et al.

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