Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1996-06-10
2000-03-28
Tsai, Jey
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438738, 438717, 438782, 430312, 430323, H01L 21302
Patent
active
060431644
ABSTRACT:
A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.
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Hsu Sheng Teng
Maa Jer-shen
Nguyen Tue
Peng Chien-Hsiung
Ulrich Bruce Dale
Gurley Lynne A.
Rabdau Mathew D.
Ripma David C.
Sharp Laboratories of America Inc.
Tsai Jey
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