Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2011-04-12
2011-04-12
Luu, Pho M (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189070, C365S233130, C365S233160, C365S233170, C365S233180
Reexamination Certificate
active
07924637
ABSTRACT:
Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).
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Askar Tahsin
Hamilton Thomas H.
Housty Oswin
Searles Shawn
Advanced Micro Devices , Inc.
Bui Tha-O
Luu Pho M
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