Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2001-03-14
2002-05-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189090
Reexamination Certificate
active
06385097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for sensing memory devices, and more particularly to a method for tracking metal bit line coupling effect.
2. Description of the Prior Art
Memory devices, such as random access memory (RAM), read-only only memory (ROM), non-volatile memory (NVM) and the like, are known in the art. Particularly, memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. These devices provide an indication of the data which is stored therein by providing an output electric signal. A device called a sense amplifier is used for detecting the signal and determining the logical content thereof.
In general, sense amplifiers determine the logical value stored in a cell by comparing the output of the cell with a reference signal. If the output is above the reference signal, the cell is determined to be erased (with a logical value of 1), and if the output is below the reference signal, the cell is determined to be programmed (with a logical value of 0). The reference signal level is typically set as a voltage level between the expected erased and programmed voltage levels which is sufficiently far from both expected voltage levels so that noise on the output will not cause false results.
Memory devices such as read-only memories ordinarily comprise an array of memory cells. Each column in the array is connected to a bit line, and each row in the array is connected to a word line. Data is read by placing electric signals on the appropriate word lines and bit lines via address decoders. In a read procedure, one of the two selected bit lines is defined as a source and the other is defined as a drain from which the content of the cell will be read. The read-out operation is a process of comparing amounts of currents flowing through a reference cell and a memory cell by using a sense amplifier after making currents flow through the reference cell and a selected memory cell and outputting data output from the sense amplifier to a data buffer.
However, as the density of integration getting higher and higher, the distance between adjacent bit lines is becoming closer and closer. Coupling occurred due to capacitance between adjacent bit lines is becoming more and more significant and non-negligible. Accordingly, the portion of the relevant data signal (programmed or erased) within the overall detected signal is significantly small. The detected signal is usually less than 100 mV, but the variation of signal caused by the bit line coupling is within the range of several 10 s mV. To reduce the coupling between adjacent bit lines, no matter by extending the distance between adjacent bit lines, which also reduces the density of integrated circuit, or by staggering the operation time of adjacent bit lines, which prolongs the operation time, is a trade off. Hence, the recurring task in memory sensing scheme is to track the coupling effect between adjacent bit lines.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for tracking metal bit line coupling effect. The present invention substantially prevents from false results due to bit line coupling in the read-out operation of a memory device and reduces bit line coupling effect without any trade off of integrated density and time prolongation.
It is another object of this invention that a method for sensing a signal received from an array cell within a memory array, which induces coupling effect, is provided.
It is a further object of this invention that a method is provided for inducing coupling effect in a reference unit.
It is still another object of this invention that a method is provided for compensating the coupling effect, which is caused by adjacent bit lines, by generating metal bit line coupling in the reference unit.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a method for tracking metal bit line coupling effect in the application of sensing a signal received from an array cell within a memory array which induces coupling effect. In the read-out operation of the present invention, because the closeness of two adjacent metal bit lines, coupling effect is induced in both memory array and reference unit at the same time, so that coupling effect is compensated. The method comprises that a reference unit with a reference cell is provided, wherein the reference unit induces coupling effect. Then, the memory array and the reference unit are charged to generate a cell signal having coupling effect and a reference signal having coupling effect. Next, a sensing signal is generated from the difference of the cell signal and the reference signal, whereby the coupling effect is compensated. Furthermore, the step of generating the sensing signal from the difference of the cell signal and reference signal includes the steps of amplifying the reference signal and the cell signal, generating a difference signal representing the difference between the amplified reference signal and the amplified cell signal, and converting the difference signal to a logical signal. Therefore, precise read-out operation of data stored in a memory cell is made possible, and the reliability of the device is improved by the present invention.
REFERENCES:
patent: 5724295 (1998-03-01), Beiley et al.
patent: 5724296 (1998-03-01), Jang
patent: 0053790 (1988-03-01), None
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition pp. 550-551.
Chen Han-Sung
Hung Chun-Hsiung
Liao Kuo-Yu
Liou Ho-Chun
Macronix International Co. Ltd.
Phan Trong
Tran M.
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