Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-20
2007-11-20
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000
Reexamination Certificate
active
11074173
ABSTRACT:
A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph of the CCG may be generated.
REFERENCES:
patent: 5703798 (1997-12-01), Dhar
patent: 5883811 (1999-03-01), Lam
patent: 5946475 (1999-08-01), Burks et al.
patent: 6185723 (2001-02-01), Burks et al.
patent: 6405348 (2002-06-01), Fallah-Tehrani et al.
patent: 6601220 (2003-07-01), Allen et al.
patent: 6662149 (2003-12-01), Devgan et al.
patent: 6711534 (2004-03-01), Parashkevov
patent: 6711722 (2004-03-01), Parashkevov et al.
patent: 7103522 (2006-09-01), Shepard
patent: 7117461 (2006-10-01), Srinivasan et al.
patent: 2003/0037306 (2003-02-01), Gutwin et al.
patent: 2004/0003356 (2004-01-01), Dewey et al.
patent: 2004/0177332 (2004-09-01), Pandey et al.
patent: 2004/0230921 (2004-11-01), Hathaway et al.
Adler, “Switch-level simulation using dynamic graph algorithms”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, No. 3, Mar. 1991, pp. 346-355.
Fusco, “Symbolic transfer functions for MESFET small-signal parameter extraction”, IEE Proceedings of Circuits, Devices and Systems, vol. 138, No. 2 Apr. 1991, pp. 217-221.
Dey et al., “Circuit partitioning and resynthesis”, Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, May 13-16, 1990, pp. 29.4/1-29.4/5.
Hu et al., “Folding an array of transistors and contacts”, Proceedings of 1992 IEEE International Symposium on Circuits and Systems, vol. 6, May 10-13, 1992, pp. 2969-2972.
Shelar et al., “Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits”, IEEE/ACM International Conference on Computer Aided Design, 2001, pp. 449-452.
Klumperink et al., “Finding all elementary circuits exploiting transconductanc”, IEEE Transactions on see also Circuits and Systems II: Analog and Digital Signal Processing, Express Briefs, vol. 48, No. 11, Nov. 2001, pp. 1039-1053.
Shelar et al., “An efficient algorithm for low power pass transistor logic synthesis”, Proceedings of 7th Asia and South Pacific and the 15th International Conference on VLSI Design, 2002, pp. 87-92.
Chang et al., “Consistency Checking for MOS/VLSI Circuits”, 20th Conference on Design Automation, Jun. 27-29, 1983, pp. 732-733.
Kik Phallaka
LSI Corporation
Strategic Patent Group Inc.
LandOfFree
Method for tracing paths within a circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for tracing paths within a circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for tracing paths within a circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3876207