Method for thread caching

Details Method for thread caching Method for thread caching

2006-08-04

2008-08-12

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S108000, C711S130000, C711S147000, C711S154000, C711S003000, C709S213000, C709S214000, C709S216000

Reexamination Certificate

active

07412568

ABSTRACT:
Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.

REFERENCES:
patent: 6092154 (2000-07-01), Curtis et al.
patent: 6665704 (2003-12-01), Singh
patent: 6675261 (2004-01-01), Shandony
patent: 2007/0192545 (2007-08-01), Gara et al.

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