Method for the testing of one time programmable memories and cor

Details Method for the testing of one time programmable memories and cor Method for the testing of one time programmable memories and cor

1989-03-21

1991-04-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 36523006, 371 28, G11C 1300

Patent

active

050070266

ABSTRACT:
The disclosure relates to one time programmable or OTP memories. When they are encapsulated in plastic packages, these electrically programmable memories can no longer be erased. Hence, they cannot be programmed in order to be tested before being sold to the customer, as they have to be delivered in non-programmable state. To enable the performance of certain tests, notably speed tests, to be made, it is proposed to simulate the programming of certain cells by prohibiting the reading of these cells when they are designated by the decoder. The memory then behaves as if it had both non-programmed cells and programmed cells (the cells for which the reading voltage is inhibited), whereas they actually comprise only non-programmed cells. A very simple logic circuit enables a simulation of a checkerboard pattern of programmed and non-programmed cells.

REFERENCES:
patent: 4958324 (1990-09-01), DeVin

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