Static information storage and retrieval – Read/write circuit – Testing
Patent
1988-11-09
1990-09-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Testing
365185, 36518908, 36518903, 371 214, 371 28, G11C 1300, G06F 1100
Patent
active
049583247
ABSTRACT:
A method for testing electrically programmable memories is disclosed. To enable the measurement of the current of programmed cells and blank cells (and not only to check whether the cells are programmed or not), and to enable this measurement even after the memory has been encapsulated in a package, it is proposed herein to connect, in testing mode, the bit line of a cell to be tested with the programming terminals to which there is applied, in programming mode, the programming high voltage Vpp. A low voltage Vte is applied to this terminal in testing mode, and the current flowing between this terminal and the voltage source is measured. This current is the current of the tested cell.
REFERENCES:
patent: 4253059 (1981-02-01), Bell et al.
patent: 4502140 (1985-02-01), Proebsting
patent: 4519076 (1985-05-01), Priel
patent: 4553225 (1985-11-01), Ohe
patent: 4670878 (1987-06-01), Childers
patent: 4714839 (1987-12-01), Chung
patent: 4720817 (1988-01-01), Childers
patent: 4731760 (1988-03-01), Maini
patent: 4734885 (1988-03-01), Luich
patent: 4768194 (1988-08-01), Fuchs
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4788668 (1988-11-01), Okada
patent: 4809233 (1989-02-01), Shannon et al.
patent: 4841233 (1989-06-01), Yoshida
Hewlett-Packard Journal, vol. 34, No. 8, 902 & 1983, pp. 20-24 Amstelveen Nl; Wheeler et al., "128K-BITN MOS . . . ", p. 23.
Patent Abstract of Japan, vol. 8, No. 151, p. 286, 13 Jul. 84; JP-A-59 48 898.
P. I EEE, vol. 74, No. 5, May 1986, pp. 684-698, W. R. Moore, "A Review of Fault . . . Circuit Yield" p. 684, col. 2, ln. 22, etc.
Patent Abstract of Japan, vol. 6, No. 51, (p-108), 6 Apr. 1982, p. 150, JP-A-56,165,984.
IEEE Trans. on Comp, vol. C-35, No. 2, Feb. 1986, pp. 99-106; Rich "A Survey of Multivalved Memories" 2P.101, l.11.
IEEE Jour. of Solid-State Cir., vol. SL-11, No. 4, Aug. 1976, pp. 514-528 Heald: "Multi-Level Random-Access . . .".
Pat. Abstracts Japan, vol. 7, No. 253, 10 Nov. 1983; JP-A-58 137 181.
NEC Research and Development, No. 26, Jul. 1972.
Garcia Alfonso
Hecker Stuart N.
Plottel Roland
SGS-Thomson Microelectronics SA
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