Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-02-21
2004-07-13
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S305000, C375S354000
Reexamination Certificate
active
06763413
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for the serial transfer of data between two electronic bus stations and to a bus station for use in said method.
Electronic consumer products often can be divided in two parts. These are front end and back end. Examples of consumer electronics products with this kind of structure are all kinds of disk players like CD player (Compact Disk), MD player (Mini Disk), DVD player (Digital Versatile Disk) and all its derivatives like video CD player, CD recorder etc. With the front end user commands are received via key entries or remote control device. The commands are forwarded to the back end part where they are executed in order to attain the associated control operation. The two part structure with front and back end has the advantage that both parts can be developed independent from each other. Of course there needs to be an interface between the two sections. This interface can then be used in various applications.
A known interface for data exchange between two electronic units is the “Video 6001 DSA Interface 7003” from Philips. It is a serial bus interface which serves for the serial transfer of data between two electronic components. As usual, in each electronic units there is an interface electronic which is connected on the internal side with the internal address, data and control bus and on the external side with the bus lines of the serial bus connection. Three bus lines are required for the serial data transfer according to the Philips DSA bus description. One line is dedicated to the data signals, a second line STB and third line SCK are reserved for control purposes. In particular these lines are used for handshake signals. If a transmitter wants to send some data, it first clears the data line to indicate that it wants to transmit data. Then it waits for a low level on the ACK line set by the receiver. After this the transmitter sets the data line high and waits for a high level on ACK line from receiver, which signals the end of starting synchronisation.
After this, the transmitter sends its data to the receiver over the DATA line. Data is send in units of 16 bit data words per each transmission phase. The transmitter sets the data line according to the bit to be send. When the DATA line becomes stable, the transmitter clears the STB line to tell the receiver that the information on DATA line is valid. The receiver reads the DATA line after the STB line low status is recognised. Then the receiver clears the ACK line to let the transmitter know that the bit was read. The transmitter sets the STB line high and waits for the ACK line high status. When the ACK line becomes high, one data bit is completely transferred.
SUMMARY OF THE INVENTION
As explained above, in the Philips DSA bus protocol each bit of a data transfer is declared to be valid and acknowledged with handshake signals on STB and ACK lines. This is a first reason which makes the bus transfer relatively slow. Furthermore, for each 16 bit data transfer a relatively long starting synchronisation process needs to be done. This is a second reason which makes the data transfer rate small.
After recognising these disadvantages it is an object of the invention to provide a modified bus protocol with which higher data transfer rates can be achieved without increasing the number of bus lines.
This object is achieved with the solution described below. The new bus protocol according to the invention is based on a combination of asynchronous and synchronous serial data transmission. The bits of a data word are transferred synchronously from transmitter to receiver. This means that there are no handshake signals which accompany the transmission of each bit. Instead, the transmitter/reveiver generates the data transfer clock which is transmitted on a dedicated bus line in parallel. Thus, the sampling points for the receiver are predefined by this clock signal as in the well known synchronous serial data transfer mode. Very high data transfer rates are achievable with this type of synchronous data transfer.
In the bus protocol it is specified that a data transfer from master to slave is signalled by sending an edge signal on a bus line which is being configured to be a data line for the master. Another bus line is being configured to be a control line for transmissions from master to slave. For data transfers from slave to master a different bus line is being configured as a data line for the slave and the other bus line is being configured to be a control line for transmissions from slave to master. There is one bus line dedicated to carry clock signals, only. This is valid for both transmission directions, from master to slave and vice versa, depending on the application. With this configurations of bus lines, bus conflicts in the case that the two bus stations are trying to access the bus simultaneously at the same time point can be easily solved in the ongoing transmission without the need of repetitive transmissions.
In such a case, due to the fact that the starting edge signals dedicated to both stations are transmitted over different bus lines, it is easy to achieve that the master will always win this conflict and the slave will change its state to receipt mode during the time period associated to the starting edge signal from master. The master will then synchronise itself to the edge signal on the control line activated by the slave so that synchronous data transmission can take place. Due to the fact that reconfiguration has been performed already during the time period of the start bit it is possible to specify a relatively short fixed delay time for synchronising, i.e. selecting the right phase of the clock signal generated in the transmitter/receiver. After this time period synchronous data transmission over the data line and clock line is commenced.
Advantageously, additional embodiments of the inventive method are disclosed in the respective dependent claims.
Data transfer in the direction from slave to master can easily be made in a similar manner as data transfer from slave to master, according to the present invention.
Transmitting a 16 bit data word in two pieces from master to slave or vice versa is advantageous if 8 bit microcontrollers are used in the bus stations. The internal data bus is often only 8 bit broad, so that a 16 bit data needs to be transfer to memory with tow different bus cycles. Another advantage is that a kind of byte handshake is makes sure that each byte is transferred correctly. For example, if an error occurs during the first transmission phase, data transfer can be interrupted immediately, which allows for a faster repetition of the data transfer.
For a bus station for use in a method according to the invention it is advantageous to connect the bus line dedicated to the data signals to an external interrupt input in addition to a data input in order to assure instantaneous reaction on a starting edge signal send by another bus station. This is in particular advantageous for a slave bus station. By doing so, bus conflicts can be immediately solved within an ongoing transmission without the need to stop transmission and wait for the repetition.
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Dang Khanh
Kiel Paul P.
Shedd Robert D.
Thomson Licensing S.A.
Tripoli Joseph S.
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