Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-01-10
2006-01-10
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06984578
ABSTRACT:
The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (12a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).
REFERENCES:
patent: 5206187 (1993-04-01), Doan et al.
patent: 5498570 (1996-03-01), Becker
patent: 5578524 (1996-11-01), Fukase et al.
patent: 5972757 (1999-10-01), Ema
patent: 6104052 (2000-08-01), Ozaki et al.
patent: 6165878 (2000-12-01), Haruhana et al.
patent: 6207571 (2001-03-01), Juengling et al.
patent: 6235620 (2001-05-01), Saito et al.
patent: 6337278 (2002-01-01), Butler
Gustin Wolfgang
Kroenke Matthias
Wang Kae-Horng
Dolan Jennifer M
Infineon - Technologies AG
Thompson Craig A.
LandOfFree
Method for the production of an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for the production of an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the production of an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3543587