Method for the processing of defective elements in a memory

Details Method for the processing of defective elements in a memory Method for the processing of defective elements in a memory

1993-12-16

2000-12-05

Beausoliel, Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714710, G06F 1100

Patent

active

061580163

ABSTRACT:
A method for the repairing of defective elements of a memory in integrated circuit form, comprising redundant elements to replace defective elements, consists of the following steps:

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Goto et al "A 3.3v 12ns 16mb CMOS SRAM" 1992 IEEE International Solid-State Circuits Conference pp. 216-217.
Jain et al "A Fault Tolerant Array Processor Designed for Testability and Self-Reconfiguration" 1991 IEEE Journal of Solid State Circuits pp. 778-788.

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