Method for the monitoring of integrated circuits

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

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714 25, G06F 1100

Patent

active

061612022

ABSTRACT:
There is proposed a process for the monitoring of integrated circuits (ASICs 21, 22) in safety-critical applications, in which the ASICs (21, 22) with identical constructions are connected in parallel and simultaneously to all inputs. The ASICs (21, 22) operate closely synchronized with each other and mutually monitor each other. They carry out a comparison of interim results, end results and output data. The logic condition is monitored at different monitoring points; namely, the freely defineable interim and end results of an information processing, the suitable internal switching conditions and the internal signals at discrete scanning points in time.

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