Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2000-06-30
2002-06-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C117S089000, C117S090000, C117S095000, C117S106000, C438S488000
Reexamination Certificate
active
06406981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to semiconductor-based products and more particularly the fabrication and design of integrated circuit structures.
2. Background of the Invention
A typical integrated circuit consists of a substrate on which devices are formed in or on the substrate. Such devices include, for example, transistors and capacitors that may be interconnected with one another and/or communicate with an external source.
One common approach to making an integrated circuit is to fabricate the circuit as part of a wafer, such as a semiconductor wafer, on which multiple integrated circuits are formed simultaneously. Fabricating the circuits at the wafer level allows similar circuits to be formed at one time which tends to make the fabrication process more efficient. Once formed, the wafer is singulated into the individual dies or chips.
One current method for manufacturing silicon semiconductor wafers involves the growth of cylindrical ingots of silicon utilizing the Czochralski (Cz) process of crystal growth. In this approach, a single crystal seed is dipped into a crucible containing molten silicon and slowly withdrawn as the crystal diameter is increased to produce a cylindrical ingot. The ingot is then sliced into wafers using, for example, a multi-wire saw. A wafer sliced from the ingot may serve as a substrate for integrated circuit device fabrication.
A current trend in the integrated circuit fabrication industry is to utilize larger diameter wafers. The wafer size has increased in the past years from approximately 125 mm (five inches) to approximately 200 mm (eight inches) and is pushing to diameters greater than 200 mm (e.g., 300 mm (12 inches)). As wafer diameters become larger, the crystal growth rate (or pull rate) in producing ingots of semiconductor material by the Cz method tends to slow down. Thus, productivity is reduced. For example, the typical growth or pull rate of 200 mm ingots is about 2 mm per minute whereas 300 mm ingots growth or pull rate is reduced to about 0.8 mm per minute. As wafer diameter is pushed beyond 300 mm, the productivity according to this method is likely to decrease further.
In addition to reduced productivity, increasing wafer (ingot) diameter tends to increase the size, complexity and capital cost of crystal growth machines. For example, for 300 mm crystal growth according to the Cz method, a magnetic field must be imposed on a silicon melt in the crucible to minimize convection currents. With larger melt volumes, melt convection currents increase which can lead to enhanced crucible corrosion with the potential for causing the crystal to dislocate.
In addition to the above concerns with increasing wafer (ingot) diameter size, other factors to be considered in ingot formation include the cost of consumables, such as crucibles and graphite heating elements which tend to increase as crystal diameter is increased. In addition, increasing the growth diameter lead to heavier crystals that are more difficult to handle during growth. Finally, increasing growth diameters will tend to increase crucible corrosion that can lead to structure loss due to, for example, silica particles floating from the crucible volume to the melt-solid interface.
What is needed is a method and structure whereby the desire for large wafer diameter structures can be achieved without the corresponding problems associated with such increase by traditional crystal growth methods.
REFERENCES:
patent: 3928092 (1975-12-01), Ballamy et al.
patent: 4283837 (1981-08-01), Slob
patent: 5853478 (1998-12-01), Yonehara et al.
patent: 5885884 (1999-03-01), Jan et al.
patent: 5910019 (1999-06-01), Watanabe et al.
patent: 6032611 (2000-03-01), Asakawa et al.
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