Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1999-02-01
2000-05-23
Picardat, Kevin M.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438400, 438135, 438133, H01L 2176
Patent
active
060665424
ABSTRACT:
Component structures of, for example, IGBTs are manufactured on the respective top sides of two substrates, the substrates are thinned proceeding from their respective back sides, and, after polishing, the back sides of the thinned substrates are durably electrically conductively connected to one another by wafer bonding.
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"High Frequency 6000 V Double Gate GTOs With Buried Gate Structure," Ogura et al, Proc. Of 1990 Int. Symp. On Power Semiconductor Devices & ICs, Tokyo, pp. 252-255.
"Bubble-Free Silicon Wafer Bonding In A Cleanroom Environment," Stengl et al, Japanese Journal of Applied Physics, vol. 27, No. 12, Dec. 1988, pp. L2364-L2366.
Eckhard Wolfgang
Reznik Daniel
Schulze Hans-Joachim
Collins Deven M.
Picardat Kevin M.
Siemens Aktiengesellschaft
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