Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1999-02-17
2002-03-12
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing control
Branching
C710S262000, C710S264000
Reexamination Certificate
active
06356998
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of microprocessors, and, more particularly, to interrupts in a microprocessor.
BACKGROUND OF THE INVENTION
Interrupts are used for reporting an event to a microprocessor. When an interrupt is received by the microprocessor, it interrupts the execution of the program in progress, saves the value of the instruction counter in a stack, and then executes a processing routine corresponding to this interrupt. After this processing routine, the execution of the program is resumed starting from the value saved in the stack.
Conventionally, the microprocessor includes several interrupt inputs that enable the microprocessor to receive several interrupts at a time. There is an order of priority between these different interrupts. When two interrupts arrive simultaneously, the interrupt having the highest hierarchical priority is processed first. The order of priority of the interrupts is generally determined by hardware circuits in an interrupt controller of the microprocessor. Furthermore, some of these interrupts are maskable, i.e. the microprocessor is not effected by these interrupts.
Management of the interrupts in a microprocessor can be accomplished in two modes. In a first mode, commonly called a “concurrent mode”, execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt even if it has priority. The new interrupt is then placed in a pending state. Only a non-maskable interrupt is capable of interrupting execution of an interrupt routine in progress.
During this mode, the microprocessor is not effected by the arrival of any new interrupts, except for the non-maskable interrupts. The masking bit is contained in a state register of the microprocessor, and is set at a 1 as soon as the interrupt is received by the microprocessor. The masking bit remains at a 1 during the processing of the interrupt. The masking bit is often called an I bit. This setting at a 1 is done by hardware. When there is no interrupt, this bit is at a 0. Furthermore, if the microprocessor receives a non-maskable interrupt during the processing of an interrupt that is maskable, the non-maskable interrupt is processed immediately by the microprocessor without this bit being taken into account.
The contents of the instruction counter and of the state register are saved in the stack as in the case of a standard interrupt. This mode is the default mode of operation for the microprocessor, and is hereinafter called mode A. The state register of the microprocessor includes, in addition to the masking bit, flags on the state of the microprocessor. This register, in particular, includes flag C which is set at a 1 when the carry value exceeds the most significant bit of the operands during an addition. Flag Z is set at a 1 if the result of the operation is a 0, and flag N is set at a 1 when the result is negative.
In a second mode of operation, commonly called the “nested mode”, the arrival of an interrupt with a higher priority than the ongoing one interrupts the processing of this ongoing interrupt. Processing is resumed only after the processing of the priority interrupt is completed. This mode makes it possible to overlap the interrupts, and is hereinafter called mode B. To implement this mode, it is generally planned after reception of an interrupt to set the masking bit at a 1 by the hardware, and then to reset it at a 1 by software.
Management of the interrupts during this mode operates as follows. During the execution of the main program, the masking bit is at 1 and the microprocessor is then in a state enabling it to process any possible interrupt as soon as it is received. When an interrupt IT
1
is received by the microprocessor, the contents of the instruction counter and of the state register of the microprocessor are saved in the stack. The masking bit is set at a 1 by hardware. The instruction counter is loaded with the interrupt vector corresponding to the interrupt IT
1
. The routine corresponding to the interrupt IT
1
is then executed. In order that the upcoming priority interrupts be processed immediately, the masking bit is set at a 1 by the software.
If a second interrupt IT
2
with a higher priority appears at the interrupt inputs of the microprocessor during the processing of the interrupt IT
1
, the contents of the instruction counter and those of the state register are saved in the stack. The instruction counter is loaded with the interrupt vector corresponding to the interrupt IT
2
. The routine corresponding to the interrupt IT
2
is executed. Once this routine is completed, the last value of the stack is restored. The execution of the interrupt routine IT
1
is continued until its end. Then the stack is again restored and the execution of the main program is continued.
There also exist microprocessors in which the order of priority is double, i.e., in addition to the circuits used to define a fixed order of hardware priority, the interrupt controller includes a software modification of this order of priority. Hereinafter in the description, a hardware priority will be understood to mean a priority achieved by hardware circuits, and a software priority will be understood to mean a priority achieved by a program.
Operation of this type of microprocessor is as follows. If the microprocessor receives an interrupt, a comparison is made initially between its level of software priority and that of the interrupt or of the program in progress. If the level of software priority of the new interrupt is higher, the interrupt routine or the program in progress is interrupted. The masking bit of the microprocessor is set at a 1 so that the priority interrupt is processed immediately. If not, the new interrupt is placed in a pending state. Thus, in order that the microprocessor may operate in mode A, it is sufficient that all the interrupts should have the same level of software priority. If this is not the case, the microprocessor operates in mode B.
The mode of operation of this type of microprocessor is therefore dictated by the software priority. This type of microprocessor is especially appropriate when the operation of the microprocessor has to be customized for the requirements of an application. However these microprocessors, with or without software priority, require a software step for the zero-setting of the masking bit after it has been set at a 1 by the hardware to operate in mode B.
SUMMARY OF THE INVENTION
It is an object of the invention to reduce the number of operations to be performed for the microprocessor to operate in mode B, i.e., an overlapping mode. In particular, the software step that places the masking bit at a 1 for reducing the time needed for the management of the interrupts in mode B is eliminated.
Another object of the invention is to provide a method for the management of interrupts in a microprocessor. The interrupts have a two-fold order of priority, i.e., a software priority and a hardware priority. The microprocessor operates in two modes. A first mode executes an interrupt routine which cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this interrupt is non-maskable. In a second mode, the execution of an interrupt routine is interrupted by the arrival of a priority interrupt.
The mode of operation of the microprocessor is conditioned by the software priority level of the interrupts. At the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor. This loading operation replaces the two-fold operation for the one-setting of the masking bit by hardware and its zero-setting by software. This operation is performed automatically by hardware circuits.
Execution of an interrupt routine in progress is interrupted by the arrival of a new interrupt when the software priority level of this new interrupt is greater than that of the interrupt in progress. Thus, the software priority modifies the order of hardware priorities and informs the microprocessor whether or not
Jorgenson Lisa K.
Niebling John F.
STMicroelectronics S.A.
Whitmore Stacy A
LandOfFree
Method for the management of interrupts in a microprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for the management of interrupts in a microprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the management of interrupts in a microprocessor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2868705