Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1998-09-30
2004-03-02
Vo, Peter (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S825000, C337S297000, C337S198000, C337S160000
Reexamination Certificate
active
06698086
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for the linear configuration of metallic fuse sections, which have a bit combination that represents a characteristic of a circuit on a wafer.
The setting of circuit characteristics, for example delay times and oscillator frequencies, is carried out on finished wafers by, inter alia, the burning of fuses. Metallic fuse sections which become severed upon burning, in that case are firstly buried under a polyimide passivation layer which is removed by exposure and subsequent etching above the fuses. It is only after the polyimide layer has been removed that it is possible to burn a fuse lying below it. Under optimum process conditions, the structuring of the polyimide layer takes place as desired, so that all of the fuse sections can be severed. However, under unfavorable conditions it may occur that the polyimide layer is not removed throughout the desired region. Fuse sections which are then still buried under polyimide cannot be burnt, i.e. severed. Since the status of a bit is dictated by the state of a fuse section, i.e. whether or not it has been severed, and the bits form the characteristic by that combination, deviations may occur between the value communicated to the circuit by burning the fuses and the target value, that is to say the characteristic. In that case, the relative deviation of the characteristic depends, on one hand, on the number of affected fuse sections which it has not been possible through error to sever, and on the other hand on the significance of the bits which are assigned to those fuse sections. In that context, the significance of a bit is intended to mean the number which, if the bit is “1”, contributes to the number to be formed in the scope of the bit combination. That will be illustrated with reference to the example of forming the number 21 by bit combination in the binary number system.
The relevant formula is:
number
=
∑
i
=
1
n
Bit
i
·
2
i
-
1
The significance of Bit
i
is thus 2
i−1
For the number 21, this means:
21=Bit
1
·2
0
+Bit
2
·2
1
+Bit
3
·2
2
+Bit
4
·2
3
+Bit
5
·2
4
=1·2
0
+0·2
1
+1·2
2
+0·2
3
+1·2
4
Thus, for example, the significance of bit
5
is 2
4
=16. When the number 21 is being formed by bit combination, bit
5
is to be taken as the most significant bit, and bit, is to be taken as the least significant bit.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for the linear configuration of metallic fuse sections on wafers, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and in which the fuse sections, due to their bit combination, represent a characteristic of a circuit on a wafer, so that even in the event of unsatisfactory adherence to process parameters and insufficient removal of polyimide on the metallic fuse sections, a resulting relative error in the characteristic of the circuit is minimized.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the linear configuration of metallic fuse sections having a bit combination representing a characteristic of a circuit on a wafer, which comprises providing a fuse section corresponding to the most significant bit; and placing other fuse sections adjacent both sides of the fuse section corresponding to the most significant bit.
The fuse section corresponding to the most significant bit is thus not located at one end of the linear configuration of metallic fuse sections. As studies have shown, when the process parameters are not adhered to satisfactorily, it is precisely at the ends of elongate regions, having surfaces which are to be rid of polyimide structures, that insufficient removal of the polyimide often occurs, for example as a result of rounding. However, with a configuration of the metallic fuse sections according to the invention, should the process parameters not be adhered to correctly and should insufficient polyimide removal take place, the fuse section which corresponds to the most significant bit will at first not be affected thereby. The fuse section corresponding to the most significant bit will not be compromised unless large deviations from the specified process parameters take place. It is thus possible to minimize the effects of unsatisfactory adherence to process parameters in a surprisingly simple way. In cases in which components could only be rejected with a conventional procedure, components are now obtained in which the circuit characteristics deviate minimally from the target value. On one hand, these components in many cases can still be sold, and on the other hand, in subsequent quality controls, conclusions may be drawn regarding insufficient polyimide removal on the basis of the particular characteristic deviations.
In accordance with another mode of the invention, the metallic fuse section corresponding to the most significant bit is located essentially in the middle of the linear configuration of the metallic fuse sections. Since the metallic fuse section which corresponds to the most significant bit and therefore makes the greatest contribution to forming the characteristic, is essentially located in the middle of the linear configuration, it is maximally removed from the ends of the elongate region which is rid of the polyimide applied to the wafer. With regard to photolithography, it is in particular the corner regions of structures which are to be rid of polyimide that are affected by deviations from the specified process parameters and the resulting reduction in polyimide ablation. Therefore, the middle of an elongate region must be regarded as particularly reliable in terms of full polyimide removal. Therefore, this configuration makes it particularly improbable that the most significant bit of the characteristic will be compromised due to errors in the polyimide structuring.
In accordance with a further mode of the invention, the fuse section corresponding to the least significant bit is located at one end of the linear configuration. Thus, if the polyimide removal is insufficient, it is firstly the fuse section which corresponds to the least significant bit, or the fuse section located at the other end of the linear configuration of fuse sections, that is affected thereby, which in the former case minimizes the relative deviation from the target value.
In accordance with a concomitant mode of the invention, the significance of the bits assigned to the metallic fuse sections decreases, from the metallic fuse section representing the most significant bit, in the direction of the two ends of the linear configuration of metallic fuse sections. This ensures that, should a fairly high degree of insufficient polyimide removal take place starting from the corner regions, the bits of the bit combination which are affected thereby are those which make a small contribution to the characteristic to be formed, due to their low significance.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the linear configuration of metallic fuse sections on wafers, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4536949 (1985-08-01), Takayama et al.
patent: 4647906 (1987-03-01), Naylor et al.
patent: 4703389 (1987-10-01), Scott
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4985866 (1991-01-01), Nakaizumi
patent: 195 48 984 (1996-07-01), None
patent: 0 327 078 (1989-08-01), None
patent: 2177562 (1987-01-01), None
patent: 2177562 (1997-01-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Trinh Minh
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