Method for the formation of an integrated electronic circuit...

Details Method for the formation of an integrated electronic circuit... Method for the formation of an integrated electronic circuit...

2006-05-26

2009-02-24

Chen, Kin-Chan (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S725000

Reexamination Certificate

active

07494932

ABSTRACT:
An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.

REFERENCES:
patent: 5981150 (1999-11-01), Aoki et al.
patent: 6756286 (2004-06-01), Moriceau et al.
patent: 2003/0042627 (2003-03-01), Farrar et al.
patent: 2004/0104448 (2004-06-01), Marty et al.
patent: 2005/0176222 (2005-08-01), Ogura
patent: 2005/0208696 (2005-09-01), Villa et al.
patent: 2005/0287767 (2005-12-01), Dantz et al.
Sato, et al., “A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration;” Electron Devices Meeting, 1999; Piscataway, NJ, USA, IEEE, US, Dec. 5, 1999, pp. 517-520; XP010372210; ISBN: 0-7803-5410-9.
Sato, et al., “SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) Technique for SoC Applications;” International Electron Deivces Meeting 2001; IEDM; Technical Digest, Washington, DC, Dec. 2-5, 2001, New York, NY; IEEE, US Dec. 2, 2001, pp. 37.1.1-37.1.4; XP010575245; ISBN 0-7803-7050-3.
Preliminary French Report, FR 0505883, dated Feb. 15, 2006.

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