Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
1999-12-10
2001-09-25
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S488000, C438S509000
Reexamination Certificate
active
06294442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device fabrication methods and, in particular, to methods for the formation of polysilicon layers of controlled, small silicon grain size.
2. Description of the Related Art
Polysilicon layers are frequently employed as the gate electrode in metal-oxide-semiconductor (MOS) devices. See S. Wolf,
Silicon Processing for the VLSI Era, Volume
2
—Process Integration,
Lattice Press, 318-319 (1990) and U.S. Pat. Nos. 5,147,813 and 5,229,631 to Been-Jon Woo. As the width of such a polysilicon gate electrode is reduced to 0.18 &mgr;m and beyond, and its height is reduced to 1500 angstroms and below, the morphology (e.g., silicon grain structure) of the polysilicon layer becomes increasingly important in determining various characteristics of the MOS device. Characteristics that can be affected by the silicon grain structure of a polysilicon layer include (i) depletion of dopant in the polysilicon gate electrode due to channeling during ion implantation, as well as dopant diffusion effects in the polysilicon gate electrode; and (ii) boron penetration through the polysilicon gate electrode during ion implantation and a consequent reduction in the integrity of a gate silicon dioxide layer that underlies the polysilicon gate electrode. Furthermore, the relatively high surface roughness of polysilicon layers can be detrimental to the photolithographic patterning processes used in semiconductor device fabrication.
The average surface roughness of as-deposited amorphous silicon layers is known to be lower than the average surface roughness of as-deposited polysilicon layers. In addition, the amorphous nature of these silicon layers reduces channeling during ion implantation. As-deposited amorphous silicon layers are, however, typically subjected to numerous thermal cycles during subsequent semiconductor fabrication processes. These thermal cycles can convert the as-deposited amorphous silicon layer into a polysilicon layer of uncontrolled and relatively large silicon grain size. The growth and morphology of polysilicon and amorphous silicon layers have, therefore, been the subject of extensive investigation. See, for example, M. T. Duffy, et al.,
LPCVD Polycrystalline Silicon. Growth and Physical Properties of Diffusion-Doped, Ion-Implanted, and Undoped Films,
RCA Review, Vol. 44, 313-325 (1983); G. Harbeke et al.,
Growth and Physical Properties of LPCVD Polycrystalline Silicon Films,
J. Electrochem. Soc., Vol. 131, No. 3, 675-682 (1984); J. Morgiel et al.,
In Situ HREM Observations of Crystallization in LPCVD Amorphous Silicon,
Mat. Res. Soc. Symp. Proc. Vol. 182, 191-194 (1990); O. S. Panwar et al.,
Comparative Study of Large Grains and High Performance TFTs in Low Temperature Crystallized LPCVD and APCVD Amorphous Silicon Films,
Thin Solid Films 237, 255-267 (1994); and J. Lutzen et al.,
Structural Characterization of Ultrathin Nanocrystalline Silicon Films Formed by Annealing Amorphous Silicon,
J. Vac. Sci. Technology B 16(5), 2802-2805 (1998) for further discussions of the subject.
The use of recrystallized amorphous silicon layers as polysilicon gate electrodes has been reported in the literature. See Shimizu et al.,
Gate Electrode Engineering by Control of Grain Growth for High Performance and High Reliable
0.18 &mgr;m
Dual Gate CMOS,
1997 Symposium on VLSI Technology, Digest of Technical Papers, 107-108 (1997). However, the relatively high temperatures and long time periods that were employed for recrystallization of the amorphous silicon layers (for example, 850° C. for 20 minutes and 610° C. for 3 hours) can lead to unwanted dopant redistribution in an underlying semiconductor substrate and the formation of undesirably large silicon grains in the resulting polysilicon layer.
Still needed in the field, therefore, is a process for controlling the grain size of polysilicon layers during semiconductor device manufacturing that is compatible with conventional semiconductor device fabrication techniques.
SUMMARY OF THE INVENTION
The present invention provides a process for the formation of a polysilicon layer with a controlled, small silicon grain size during semiconductor device fabrication. The controlled, small silicon grain size (for example, less than 50 nm for a 0.18 &mgr;m process technology and less than 30 nm for a 0.10 &mgr;m process technology) decreases channeling through the polysilicon layer during subsequent ion implantation processes. Such a decrease in channeling provides for a beneficial reduction in boron penetration and, therefore, an increase in gate silicon dioxide layer integrity. The presence of small silicon grains in the polysilicon layer is also believed to provide for a desirable reduction in polysilicon dopant depletion effects.
Processes according to the present invention include steps of first providing a semiconductor substrate (e.g., a silicon wafer), followed by the formation of a silicon dioxide layer (e.g., a gate silicon dioxide layer) thereon. Next, an amorphous silicon layer is deposited on the silicon dioxide layer. A plurality of silicon crystallites are then formed in the amorphous silicon layer by subjecting it to a first thermal cycle. Finally, the amorphous silicon layer and silicon crystallites therein are subjected to at least one additional thermal cycle, thereby growing the silicon crystallites into small silicon grains and converting the amorphous silicon layer into a polysilicon layer with controlled, small silicon grain size.
In one embodiment of processes according to the present invention, a semiconductor substrate is first provided, followed by the formation of a gate silicon dioxide layer thereon. An amorphous silicon layer is then deposited on the gate silicon dioxide layer using a low pressure chemical vapor deposition technique at a temperature in the range of 520° C. to 560° C. and a pressure in the range of 150 mTorr to 250 mTorr. The amorphous silicon layer has a typical thickness in the range of 1000 angstroms to 2500 angstroms. A plurality of silicon crystallites (i.e., small silicon grains) are subsequently formed in the amorphous silicon layer by subjecting the amorphous silicon layer to a first thermal cycle that includes a temperature ramp rate of at least 50° C. per second and an annealing step at a temperature in the range of 740° C. to 760° C. for a time period of 30 seconds to 90 seconds. The amorphous silicon layer with silicon crystallites therein is then patterned to form a patterned amorphous silicon layer still containing silicon crystallites therein. The patterned amorphous silicon layer includes silicon gate electrodes with a width in the range of 0.10 &mgr;m to 0.25 &mgr;m. Finally, the patterned amorphous silicon layer with silicon crystallites is subjected to at least one additional thermal cycle. The additional thermal cycle grows the silicon crystallites into small silicon grains and converts the amorphous silicon layer into a polysilicon layer with controlled, small silicon grain size in the range of 20 nm to 50 nm.
In processes, according to the present invention, an amorphous silicon layer is subjected to a first thermal cycle (for example, using a rapid thermal anneal [RTA] process that does not alter dopant distribution in the underlying semiconductor substrate) in order to form small silicon crystallites in the amorphous silicon layer. The amorphous silicon layer retains the low surface roughness (e.g., no more than 15 angstroms of rms surface roughness or less than 1% of the amorphous silicon layer thickness) required for photolithography even after the first thermal cycle. Upon being subjected to at least one additional thermal cycle during subsequent semiconductor device fabrication, such as silicon dioxide sidewall spacer formation, silicon nitride sidewall spacer formation, or dopant activation processes, the silicon crystallites grow into small silicon grains. In essence, the silicon crystallites act as seeds for the formation of small silicon grains during these subseq
Bowers Charles
Girard & Equitz LLP
National Semiconductor Corporation
Sarkar Asok Kumar
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