Method for the formation of a boron-doped silicon gate layer...

Details Method for the formation of a boron-doped silicon gate layer... Method for the formation of a boron-doped silicon gate layer...

1999-10-04

2001-06-05

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S592000, C438S649000

Reexamination Certificate

active

06242348

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device fabrication and, in particular, to processes for forming a boron-doped silicon gate layer underlying a cobalt silicide layer.
2. Description of the Related Art
The fabrication of semiconductor devices involves the processing of a semiconductor substrate (e.g. a silicon wafer) through a series of steps, including multiple ion implantation processes. During such an ion implantation process, dopant atoms are introduced into, and below, the surface of the semiconductor substrate and into various layers (e.g. a polysilicon gate layer) which have been formed on the semiconductor substrate. The dopant atoms are added to the semiconductor substrate to form various device regions, such as well regions, Lightly Doped Drain (LDD) extension regions, and source and drain regions. The dopant atoms are also introduced into the semiconductor substrate to modify the electrical characteristics of the semiconductor device; for example, to reduce the sheet resistance of a polysilicon gate layer. See S. Wolf and R. N. Tauber,
Silicon Processing for the VLSI Era, Volume
1
—Process Technology,
pp. 280-283, Lattice Press (1986), which is hereby incorporated by reference, for a further discussion of ion implantation processes.
In Metal-Oxide-Semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as “salicide” layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drains regions, as well as contact resistance. See, for example, Stanley Wolf,
Silicon Processing for the VLSI Era,
Vol. I, 388-399 (Lattice Press, 1986).
Referring to
FIG. 1
, a representative conventional PMOS transistor structure
10
is illustrated. Conventional PMOS transistor structure
10
includes a gate oxide layer
12
overlying N-type silicon substrate
14
between P-type drain region
16
and P-type source region
18
, both of which are formed in N-type silicon substrate
14
. A conventional PMOS transistor structure
10
also includes a boron-doped polysilicon gate layer
20
overlying gate oxide layer
12
. Gate sidewall spacers
24
, typically formed of silicon dioxide or silicon nitride, are disposed on the lateral surfaces of boron-doped polysilicon gate layer
20
and gate oxide layer
12
. Conventional PMOS transistor structure
10
further includes cobalt silicide layers
32
,
34
and
36
on the drain region
16
, the source region
18
and the boron-doped polysilicon gate layer
20
, respectively.
The drawbacks of conventional processes used to fabricate PMOS transistor devices include (i) increased risk of boron dopant penetration into and through the gate oxide layer as fabrication processes progress to 0.10 &mgr;m devices and (ii) instability of the cobalt silicide layers (for example, agglomeration and “grooving” of the cobalt silicide layer along polysilicon grain boundaries in the boron-doped polysilicon gate layer). Boron dopant penetration can degrade the performance of PMOS transistor devices by causing a flat-band voltage shift, and an increase in both sub-threshold swing and leakage current. Boron dopant penetration from the boron-doped polysilicon gate layer into the gate oxide layer can also deteriorate the quality of the gate oxide layer. Further, cobalt silicide, which comes into contact with the gate oxide layer via a “grooving” mechanism, can have a detrimental effect on semiconductor device fabrication yield.
Semiconductor device fabrication processes which employ implantation of BF
2
+ into a CoSi/amorphous silicon bilayer have been reported to be effective in suppressing boron penetration in PMOS devices. See W. K. Lai, et al., A Novel Process to Form Cobalt Silicided p
+
Poly-Si Gates by BF
2
+
Implantation into Bilayered CoSi/a-Si Films and Subsequent Anneal, IEEE Electron Device Lett., Vol. 19, 259 (1998), which is hereby incorporated by reference. The use of CoSi layer as an implantation barrier and as a diffusion source has also been shown to be effective in reducing boron diffusion during the formation of shallow junction regions (e.g. source and drain regions). See M. H. Juang, et al., Shallow Junctions Formed by BF2
+
Implantation into Thin CoSi Films and Rapid Thermal Annealing, J. Appl. Phys., vol. 76, 323, (1994), and H. C. Cheng, et al., “A Silicidation-Induced Process Consideration for Forming Scale-down Silicided Junction,” IEEE Electron Device Lett., vol. 15, no. 9, 342 (1994), both of which are hereby incorporated by reference.
Significant improvement in the thermal stability of CoSi
2
layers can be achieved by implanting low energy (e.g. 20 KeV) BF
2
+
into CoSi
2
layers formed on as-deposited amorphous silicon gate layers (300 nm), compared to CoSi
2
layers formed on as-deposited polysilicon gate layers. See Wei-Ming Chen, et al., Thermal Stability and Dopant Drive-out Characteristics of CoSi
2
Polycide Gates, J. Appl. Phys., vol. 73, p. 4712, (1993), which is hereby incorporated by reference.
Nitrogen implantation prior to cobalt layer deposition has been reported to suppress CoSi
2
agglomeration during subsequent cobalt silicide formation. For example, the thermal stability of a cobalt silicide layer disposed on a p-type doped polysilicon gate layer has been reported to be dramatically improved, if N
2
+
is implanted into the p-type doped polysilicon layer prior to cobalt layer deposition and cobalt silicide formation. See Wein-Town Sun et al., Suppression of Cobalt Silicide Agglomeration Using Nitrogen (N
2
+
) Implantation, IEEE Electron Device Lett., vol. 19, 163 (1998), which is hereby incorporated by reference.
None of the reported processes, however, provide a method for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that simultaneously minimizes grooving and agglomeration of cobalt silicide layer, as well as boron dopant penetration into and through a gate oxide layer. There is, therefore, still a need in the art for such a process.
SUMMARY OF THE INVENTION
The present invention provides processes for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that simultaneously minimizes grooving and agglomeration of cobalt silicide layer, as well as boron dopant penetration into and through the gate oxide layer. A process according to the present invention includes first providing a PMOS transistor structure including an N-type silicon substrate, a gate oxide layer on the silicon substrate, and a silicon gate layer (e.g. an amorphous silicon gate layer or a polysilicon gate layer) overlying the gate oxide layer. A cobalt layer is then deposited on the PMOS transistor structure. The PMOS transistor structure and the cobalt layer are subsequently subjected to a first thermal treatment at, for example, a temperature of 500° C. to 550° C. in order to form a bilayer CoSis/silicon stack structure. After removal of any unreacted cobalt, boron dopant (e.g., BF
2
+
or B
+
) is implanted into the bilayer CoSi/silicon stack structure. Nitrogen atoms (e.g. N
2
+
) are then implanted into the bilayer CoSi/silicon stack structure. Finally, the bilayer CoSi/silicon stack structure, implanted boron dopant and implanted nitrogen atoms are subjected to a second thermal treatment at, for example, a temperature of 800° C. to 950° C. in order to form a CoSi
2
layer. The second thermal treatment is also designed to thermally activate the implanted boron dopant, thereby forming a boron-doped silicon gate layer underlying a cobalt silicide (CoSi
2
) layer. The presence of nitrogen atoms in the bilayer CoSi/silicon stack structure suppresses grooving and agglomeration of the cobalt silicide layer during the second thermal treatment step. In addition, the CoSi layer of the CoSi/silicon stack structure serves as a boron dopant implantation barrier that significantly reduces the risk of boron dopant penetration into and through the gate oxide layer.
Also provided by the present invention is a process

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