Method for the etching of a heterostructure of materials of the

Details Method for the etching of a heterostructure of materials of the Method for the etching of a heterostructure of materials of the

1993-11-05

1995-05-02

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566431, 1566621, 1566561, 1566461, 1566491, 437909, H01L 2100

Patent

active

054116325

ABSTRACT:
Disclosed is a method for the etching of at least two layers of semiconductor materials having different natures, with a view to making a mesa for the self-alignment of the metallizations of a transistor. The heterojunction must comprise a first layer of a material containing As, which is etched by reactive ion etching, and a second layer of a material containing P which is etched chemically. Application to the making of HBT type vertical heterojunction transistors.

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patent: 5111265 (1992-05-01), Tanaka
patent: 5330932 (1994-07-01), Liu et al.
Proceeding of the Inter. Electron Devices Meeting 1987, Dec. 6, 1987, pp. 852-853, H. Schumacher, et al., "OMCVD Grown InP/InGaAs Heterojunction Bipoplar Transistors".
IEEE Electron Device Letters, vol. EDL-7, No. 6, Jun. 1986, pp. 359-362, R. Fischer, et al., "Reduction of Extrinsic Base Resistance in GaAs/AlGaAs Heterojunction Bipolar Transistors and Correlation with High-Frequency Performance".
Applied Physics Letters, vol. 53, No. 11, Sep. 12, 1988 pp. 983-985, W. T. Tsang, et al., "GaInAs/GaInAsP/InP Heterostructure Bipolar Transistors with Very Thin Base (150 A) Grown by Chemical Beam Epitaxy".

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