Method for the erasure of memory cells, device designed to imple

Details Method for the erasure of memory cells, device designed to imple Method for the erasure of memory cells, device designed to imple

1990-05-30

1992-08-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Erase

365185, G11C 700

Patent

active

051385805

ABSTRACT:
A method for erasure of EEPROM memory cells consists, at the start of each erasure operation, in opening a counter in a RAM memory, carrying out a cycle of erasure as stipulated by the manufacturer, and then a cycle for reading and for comparing the voltage read with an expected voltage corresponding to the "erased" state of the memory cell. Then, if the voltage read is not the expected voltage, in incrementing the counter and ordering a new cycle of erasure, reading and comparison. When the voltage read is the expected voltage, a return code characteristic of the content of the counter and, hence, of the number of erasure cycles that have been necessary for the erasure operation, is transmitted to the user. The method can be applied, notably, to EEPROM memory devices used chip cards.

REFERENCES:
patent: 4680736 (1987-07-01), Schrenk
patent: 4758986 (1988-07-01), Kuo
patent: 4763305 (1988-08-01), Kuo
Patent Abstracts of Japan vol. 2 No. 65 p. E 78 May 18, 1978.
Patent Abstracts of Japan vol. 7 No. 42 (P-177) [1187] Feb. 19, 1983.

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