Method for the continuous readout of a data sequence from a memo

Details Method for the continuous readout of a data sequence from a memo Method for the continuous readout of a data sequence from a memo

1997-12-03

2000-06-06

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711106, 711157, 711173, 711168, 365222, 36523003, G06F 1206

Patent

active

060732032

ABSTRACT:
For the continuous and interruption-free readout of a data sequence predetermined by a predetermined address sequence from a memory that is constructed of dynamic memory components (DRAM or SDRAM) and that is divided into a number of separately addressable memory banks, the control circuit controlling the readout of the data sequence from the memory cells is operated, and the distribution of the data in the memory cells of the banks is selected, such that another bank is respectively refreshed during the readout of data from one of the banks. The memory contains at least three memory banks and the sequence of the bank addresses is always selected such that, given access to a bank, at least the access onto the preceding bank did not exhibit the same bank address.

REFERENCES:
patent: 5161221 (1992-11-01), Van Nostrand
patent: 5206944 (1993-04-01), Pilkenton
patent: 5265231 (1993-11-01), Nuwayser
patent: 5274788 (1993-12-01), Koike
patent: 5561784 (1996-10-01), Chen et al.
patent: 5572691 (1996-11-01), Koudmani
patent: 5706407 (1998-01-01), Nakamura
Fast DRAMs Can Be Swapped For SRAM Caches, Bursky, Electronic Design 22, Jul. 22, 1996, pp. 55-70.

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