Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-31
1999-10-26
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711128, 711135, 711145, 714 42, G06F 1208
Patent
active
059745100
ABSTRACT:
A method for testing the functioning of a non-cacheable region within a cache having a cache controller programmed with a write-back write policy and a non-cacheable region included in an image memory region corresponding to a physical memory region. A first data pattern is written to the cache tagged at a first addressable location of a cacheable region in the physical memory region. A second data pattern is written to the cache tagged at a second addressable location in the image memory region contained within both the non-cacheable region and the cacheable region and corresponding to the first addressable location. The data stored in the cache and tagged at the first addressable location and corresponding to the non-cacheable region only of the second addressable location is read to determine whether the first data pattern remains in the cache thereby indicating that the non-cacheable region is functioning correctly. The data stored and tagged at a third addressable location in the physical memory region and corresponding to the cacheable region only of the second addressable location in the image memory region is read to determine whether the second data pattern remains in the cache tagged at the third addressable location thereby indicating that the non-cacheable region is functioning correctly and that the memory size of the non-cacheable region is correct.
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Cheng Lei
Eckert Thomas F.
Wisor Michael T.
Advanced Micro Devices , Inc.
Bragdon Reginald G.
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