Method for testing semiconductor memory devices, and apparatus a

Details Method for testing semiconductor memory devices, and apparatus a Method for testing semiconductor memory devices, and apparatus a

1997-01-23

2000-07-25

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714710, G01R 3128

Patent

active

060947330

ABSTRACT:
A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

REFERENCES:
patent: 5436559 (1995-07-01), Takagi et al.
patent: 5675544 (1997-10-01), Hashimoto
patent: 5795797 (1998-08-01), Chester et al.
patent: 5859804 (1999-01-01), Hedberg et al.
T. Satou et al., "Tester for Memories", Guidebook on Apparatuses for Manufacturing and Testing Apparatuses, Dec. 1995, pp. 148-153.

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