Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-14
2001-04-03
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C327S537000
Reexamination Certificate
active
06211689
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for testing a semiconductor device provided with a transistor circuit marking capable of causing damage which can be visually identified by latch-up to identify a chip on a wafer which has been determined as defective by a functional test, and a semiconductor device with a transistor circuit for marking.
2. Description of the Related Art
When a functional test on a wafer is conducted, it is necessary that chip determined as a defective is marked. Normally, marking of the defective chip is effected by using mechanical means such as an inker provided at a probing unit. There is the fear that a chip next to a defective chip may be erroneously marked when a marking position is shifted in a case of employing such mechanical means. There has been, thus, proposed a marking method by providing a special circuit in an LSI without using mechanical means.
FIG. 1
is a typical plan view of a semiconductor chip to describe a method for marking a semiconductor device as described in Japanese Patent Application Laid-Open No. 61-64137. This semiconductor chip
34
is provided with a marking dedicated pad
31
, a GND pad
32
and a circuit for marking
33
. The circuit for marking
33
consists of a material which can be easily fused such as aluminum. One end of the circuit
33
is connected to the marking dedicated pad
31
and the other end thereof is connected to the GND pad
32
.
In the conventional semiconductor device, when the chip is determined as a defective by the wafer functional test, the circuit for marking
33
is fused by applying a high voltage or high current to the marking dedicated pad
31
. Thereafter, the fused portion is visually identified and the defective chip is thereby screened.
Meanwhile, Japanese Patent Application Laid-Open No. 63-102332 discloses a method for identifying a defective chip wherein a thermal coloring matter or resin containing the thermal coloring matter is applied on the surfaces of chips of a semiconductor device in advance and a defective chip, if any, is colored by applying a current to the coloring matter and identified as such.
In addition, Japanese Patent Application Laid-Open No. 2-90549 discloses a semiconductor device having a memory cell for inputting and storing a case of a non-defective chip or defective.
Moreover, Japanese Patent Application Laid-Open No. 6-53292 discloses a method for inspecting a semiconductor device capable of detecting, for example, visually that a semiconductor integrated circuit part is abnormal by applying an excessive voltage to a power supply terminal of an operational check circuit part to thereby break the operational check circuit part.
Furthermore, Japanese Patent Application Laid-Open No. 9-199672 discloses a method for inspecting a semiconductor integrated circuit device having a structure in which a fuse is provided in the middle of each of the wirings connected to the first and second electrodes and to an internal circuit, a voltage exceeding input allowable level is supplied to both the first and second electrodes to disconnect the fuse, thereby stopping supplying power to the internal circuit of a defective chip.
The conventional technique described in Japanese Patent Application Laid-open No. 61-64137 has the following problems. First, if insufficient voltage or current is applied, the marking circuit
33
may not be fused. If so, a defective chip is determined as a non-defective. Second, contrary to the first, if an excessive current or voltage is applied, there is a fear of breaking not only a defective but also a chip next to the defective chip.
As for the other references stated above, the methods described therein have similar problems; i.e., if an excessive current or voltage is applied or a voltage applied is lower than an operating voltage, a defective chip may not be possibly identified. Besides, the technique of Japanese Patent Application Laid-Open No. 2-90549 has a disadvantage in that a dedicated memory cell is necessary.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for testing a semiconductor device which can ensure identifying a defective chip and which does not adversely affect chips adjacent to the defective chip, and to provide a semiconductor device with a transistor circuit for marking.
A method for testing a semiconductor device according to the present invention comprises the steps of: providing a semiconductor chip with a transistor circuit for marking; performing a functional test to the chip to determine whether the chip is a defective or not; inputting a signal for causing latch-up to occur to the transistor circuit for marking when the chip is determined as a defective and damaging the marking transistor circuit to allow the marking transistor to be visually identified.
The transistor circuit for marking can be constituted such that the circuit is a CMOS transistor circuit and has a signal terminal for test for inputting the signal for causing latch-up. In this case, the transistor circuit for marking can includes: a P-type MOS transistor and an N-type MOS transistor connected in series between a power supply pad and a ground pad; a first inverter connected to the signal terminal for test and having an output terminal connected to a drain of the N-type MOS transistor; and a second inverter into which an output signal of the first inverter is inputted and an output terminal of which is connected to a drain of the P-type MOS transistor.
In addition, a semiconductor device according to the present invention comprises: a transistor circuit for marking other than a functional circuit provided at a semiconductor chip; a test signal input terminal for inputting a signal causing latch-up to occur to the transistor circuit for marking, wherein the latch-up occurs to the transistor circuit for marking by inputting the signal into the test signal input terminal and the transistor circuit for marking is thereby damaged.
In this semiconductor device, the transistor circuit for marking can be constituted of a CMOS transistor circuit structure. In this case, the transistor circuit for marking can include: a P-type MOS transistor and an N-type MOS transistor connected in series between a power supply pad and a ground pad; a first inverter connected to the test signal terminal and having an output terminal connected to a drain of the N-type MOS transistor; and a second inverter into which an output signal of the first inverter is inputted and an output terminal of which is connected to a drain of the P-type MOS transistor.
According to the present invention, a transistor circuit for marking consisting of a transistor having particularly weak latch-up characteristics is installed on a semiconductor chip. When a wafer functional test is performed, latch-up is caused to occur to the transistor circuit for marking of a chip determined as a defective and the peripheral portion of the transistor is broken, thereby visually identifying the defective chip. Therefore, in the present invention, a signal for causing latch-up does not need to be a high voltage or high current signal. Thus, disadvantages of the conventional techniques are not produced.
REFERENCES:
patent: 5473500 (1995-12-01), Payne et al.
patent: 5721445 (1998-02-01), Singh et al.
patent: 5917689 (1999-06-01), English et al.
patent: 6023186 (2000-02-01), Kuroda
patent: 61-64137 (1986-04-01), None
patent: 63-102332 (1988-05-01), None
patent: 2-90549 (1990-03-01), None
patent: 3-196539 (1991-08-01), None
patent: 5-198630 (1993-08-01), None
patent: 6-53292 (1994-02-01), None
patent: 9-199672 (1997-07-01), None
Foley & Lardner
Metjahic Safet
NEC Corporation
Tang Minh
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