Method for testing semiconductor circuitry for operability and m

Details Method for testing semiconductor circuitry for operability and m Method for testing semiconductor circuitry for operability and m

1993-09-03

1994-07-05

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 1566591, 156662, 324500, 324724, 324754, 437 8, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

053264282

ABSTRACT:
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

REFERENCES:
patent: 4312117 (1982-01-01), Robillard et al.
patent: 4585991 (1986-04-01), Reid et al.
patent: 4952272 (1990-08-01), Okino et al.

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