Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-24
2004-02-24
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000
Reexamination Certificate
active
06697978
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the known good integrated circuits, semiconductors in general and, more specifically, to improved Known Good Die (KGD) integrated circuit semiconductor devices which include memory components such as static RAM or dynamic RAM. This invention also relates to logic or application specific integrated circuits (ASIC).
BACKGROUND OF THE INVENTION
Recent improvements to VLSI integrated circuit testing at the wafer level indicate that traditional test methods may not be optimal. Specifically, module level screens, such as time and resource consuming burn-in, temperature cycling, etc., are no longer unique in their ability to identify and eliminate latent defects.
It is well established within the test. industry that a high quality screen at the earliest point of assembly (i.e. wafer test) is typically,.economically optimal. It has been estimated that the cost of identifying and replacing defective die increase ten-fold at each level of packaging. Considering that the test cost alone can represent up to 50% of the product cost, high quality early screening, can represent a major savings. Effective die screening is especially important for Multichip Module (MCM) testing, where the ultimate MCM assembly yield is exponentially proportional to post wafer level test quality level. This fact alone may be why today's MCMs are typically populated with relatively low number of die (2 to 10). When the number of dies exceeds 10, quality levels for individual die must be well above 99% to achieve acceptable MCM yields.
Many screening options are simply not available. during wafer test. These include at-speed test, temperature testing, and testing input/outputs at worst case voltage swings. Additionally, the module level has traditionally been the first level at which reliability-oriented screens such as burn-in can be performed. It is clear that relying on such a screen at the MCM level to first identify an unreliable die poses an unacceptably high risk of unacceptable yields to the MCM manufacturer.
To address this problem, the concept of Known Good Die (KGD) was developed. This was an industry/government initiative to develop test methodologies that allowed bare die to be screened to quality levels equivalent to those quality levels available at the module level. Guidelines for insuring Known-Good-Die (KGD) in JPL Space Flight Hardware published by the Electronics Parts Engineering Office 507, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91109, D-16389, Mar. 15, 1999 describes the concept of KGD and is herein incorporated by reference. KGD's provide the highest reliability and minimum risk levels. Initially the prime method of achieving this goal was to develop temporary die attach methods which permitted module level testing and screening (e.g.) burn-in to be performed prior to die classification. Over time, however, the disadvantage of this mechanical-packaging oriented approach has become evident. It has been proven to be difficult to implement a contacting approach that can maintain a reliable. electrical contact during the rigors of burn-in, and temperature extreme testing, while not damaging the die pad surface (thus reducing the likelihood of defect free bonding during subsequent module assembly). Carriers that are capable of this delicate balance tend to either be prohibitively expensive and/or not sufficiently durable for production manufacturing. Often the cost associated with temporary attachment exceeds the cost associated with simply placing wafer level screened die directly on the MCM.
The state of the art in this area indicates that a goal of wafer-level screening is achievable. First, novel test methods have been developed for CMOS. which have been shown to enhance product reliability. These methods are used to identify defects in dies. These include quiescent current (Iddq) testing, which was originally proposed in 1981. This test method provides improved detection of bridging faults as compared to standard (i.e. stuck fault). test methods and die defects. Subsequent MCM infant mortality is, therefore, reduced. Iddq testing was subsequently shown to reduce burn-in failures by 51%. The Iddq test is used primarily to detect shorts in the circuit. If Iddq exceeds a limit, it is presumed that there are metal or conductor lines that have a short. circuit or a piece of conducting foreign material shorting two lines. If a part should be drawing a nannoamp or a microamp, and it is drawing 100 microamps, the part is obviously defective.
A defect activating stress test method can be the application of an elevated voltage (V
dd
) for a specified period of time, especially when followed by Iddq tests. This approach takes advantage of failure mechanism acceleration factors associated with higher supply voltages. Another defect detecting test method is Very Low Voltage Testing, where tests are conducted at supply voltages close to the transistor threshold voltage. By targeting defects that induce internal voltages that are not full V
dd
transitions, this methodology has the potential for detecting a variety of subtle malfunctions that could ultimately evolve into failures.
While alternative testing exists, what still remains is to select and implement the correct die test methods, given the specific attributes of the semiconductor. Each semiconductor manufacturing facility's process has its own unique defect densities and potential reliability risks. This is especially true for facilities which fabricate radiation hardened Integrated Circuits (ICs.) because these processes tend to display unique (as compared to commercial ICs) features. Additionally, given the nature of the radiation hardened ICs, high reliability is a paramount concern.
Extending successful Application Specific Integrated Circuit (ASIC) Known Good Die (KGD) approaches to Static Random Access Memories (SRAMs) is not without challenges. For instance, SRAMs display different temperature sensitivities than ASICs. SRAMs are adversely affected by both hot and cold temperatures. Cold temperature testing is not typically possible during a wafer test, because due to condensation, etc., the test chuck can raise the temperature during testing. Reducing the temperature from room temperature is, therefore, not feasible precluding the ability to verify performance under entire operating conditions. Another SRAM specific problem results from the use of redundancy to improve die yields. As standard manufacturing practice, additional memory cells are added to the SRAM. If during testing, defective memory cells are found, these cells are logically disconnected and replaced with these excess cells. These defective cells can continue to elevate the die quiescent current (Iddq) while not affecting functionality. This then complicates Iddq testing, which is an essential element of Known Good Die testing. The presence of analog circuitry within the sense amplifiers, which can elevate the quiescent current of defect-free devices so that the additional contribution of a defect cannot be detected, is also an element unique to memories which must be addressed.
Additionally large capacity static RAM cannot be tested utilizing standard Iddq testing. The reason is that static RAM may include millions of memory cells, each contributing to the sum total of Iddq. Therefore, a short or failure which would elevate the Iddq by 1 to 200 microamps is hot detectable when the defect free Iddq can be in the order of 2 milliamps.
Summary of the Invention
The term multi-pattern data retention test as used in this application refers to placement of a pattern of logical ones and zeros in a device such as a memory or a logic circuit where there are ones and zeros physically adjacent to each other. The pattern may be a checkerboard or checkerboard bar as illustrated in
FIGS. 4 and 5
or any other arbitrary pattern. The test preferably uses at least a pattern and its compliment such as checkerboard and checkerboard bar. In its simplest form, the test can
Bear Michael J.
Storey Thomas M.
BAE Systems Information and Electronic Systems Integration Inc.
Chung Phung M.
Gandhi Dipakkumar
Snider Ronald R.
Snider & Associates
LandOfFree
Method for testing of known good die does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing of known good die, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing of known good die will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3336455