Method for testing memory cell in semiconductor device

Details Method for testing memory cell in semiconductor device Method for testing memory cell in semiconductor device

2001-12-28

2003-04-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S211000, C365S185200, C365S185220

Reexamination Certificate

active

06556493

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for testing a memory cell in semiconductor device; and, more particularly, to a method for optimally testing a memory cell by setting a new trip point of a reference memory cell according to a variation of temperature.
DESCRIPTION OF RELATED ART
Generally, a predetermined test is carried out to increase reliability of a semiconductor device after a fabrication process of the semiconductor device is completed. The semiconductor devices are classified into normal goods and failed goods after the predetermined test.
Recently, as users using the semiconductor device demand reliability for wide parts of the semiconductor device, problems generated according to the conventional test of the semiconductor device become an important factor.
For example, referring to
FIG. 1
, characteristics of gate voltage Vg and a drain current Id are changed according to a temperature environment, such as a cold, room or hot temperature, when a test is carried out.
As compared with a test at a room temperature, a low drain current Id flows at low gate voltage Vg and a high drain current Id flows at high gate voltage Vg when a test is carried out at a cold temperature. As compared with a test at a room temperature, a high drain current Id flows at low gate voltage Vg and a low drain current Id flows at high gate voltage Vg when a test is carried out at a hot temperature. It is a physical phenomenon. When the gate voltage Vg is low at a hot temperature, the drain current Id is nearly a leakage current in a junction portion and, when the gate voltage Vg is high at a hot temperature, the drain current Id is nearly current flowing from a source to a drain.
Namely, when the test is carried out at a hot temperature, the drain current Id is higher at low gate voltage Vg than the drain current Id at the room temperature due to the leakage current and the drain current is lower at high gate voltage Vg than the drain current Id at the room temperature due to scattering of electrons and lattice. On the other hand, when the test is carried out at a cold temperature, an inverse characteristic is shown.
Referring to
FIG. 2
, to solve the above problem, a test carried out at a trip point, as a test operation point, which has a constant point independent of the variation of temperature. However, since the identical drain current does not always flow in memory cells in the semiconductor device, it is difficult that a reference drain current is always maintained in an identical level. The drain current Id is varied according to a characteristic of a unit cell in a memory of the semiconductor device as shown in FIG.
3
. The drain current Id may be represented as a dotted line or a solid line in
FIG. 3
according to a characteristic of each memory cell for the variation of temperature. Since the drain current Id does not identically flow at each memory cell in the semiconductor device, it is difficult that a level of the drain current Id is always maintained in the same level.
A read margin of the memory cells, of which threshold voltage Vt is different from each other, is determined by gate voltage Vg and a temperature as shown in table 1.
TABLE 1
Hot
Cold
Low Vg.
First cell
Fail
Good
Second cell
Good
Fail
High Vg.
First cell
Good
Fail
Second cell
Fail
Good
In table 1, the first cell represents that electrons do not exist in a floating gate in memory cells of the semiconductor device, which is in an erasure state, and the second cell represents that electrons exist in a floating gate in memory cells of the semiconductor device, which is a program state.
Data are read when the low gate voltage is applied to a memory cell having a different drain current characteristic (for example, a memory cell having the highest threshold voltage) at a hot temperature. Since the drain current flowing in the memory cell is not the same as the reference drain current, the trip point is moved to left as much as &Dgr;l. Accordingly, the memory cell is failed at the hot temperature. Namely, it is the same case as that data are written at the polar region and the data are read at the equatorial region.
The first cell may be failed at low gate voltage Vg and at a hot temperature and the second cell may be failed at a low gate voltage and at a cold temperature or at high gate voltage and at a hot temperature.
The method for testing a memory cell of the semiconductor device according to the prior art is that the trip point of the predetermined memory cell is set as a reference trip point and other memory cells are determined whether the memory cells are good or failed on the basis of the reference trip point. However, temperature variation is not considered and the conventional testing method has been carried out at a room temperature so that an accurate test of the memory cell in the semiconductor device cannot be expected.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for testing a memory cell of the semiconductor device capable of optimally measuring a reference drain voltage according to a test temperature and characteristics of the memory cell.
In accordance with an aspect of the present invention, there is provided a method for testing a memory cell of the semiconductor device, comprising the steps of: a) determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell; b) testing an erasure verifying memory cell to be tested at a room temperature; c) testing the erasure verifying memory cell at a hot temperature; d) programming the reference memory cell; and e) setting a second trip point by varying the first trip point.


REFERENCES:
patent: 5717632 (1998-02-01), Richart et al.
patent: 5774395 (1998-06-01), Richart et al.
patent: 6118706 (2000-09-01), Smayling et al.
patent: 6288944 (2001-09-01), Kawamura

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