Method for testing memories with seamless data input/output...

Details Method for testing memories with seamless data input/output... Method for testing memories with seamless data input/output...

2005-02-22

2005-02-22

Lamarre, Guy J (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06859901

ABSTRACT:
A method for testing memories has steps of providing seamless data to data input/output pins and providing seamless control commands to each bank at each clock cycle, when the memories receive the seamless data and control commands, and the data input/output pins of memories receive heavy loads status. For SDRAM and DDR-DRAM, control commands and data are seamlessly inputted/outputted at each clock cycle. For RDRAM, control commands are inputted at each “command packet”, whereby data are inputted/outputted at each “data packet” and memories are in the heavy loading status. By providing heavy loading to control pins and data input/output pins of memories, it is easy to detect weakened memories.

REFERENCES:
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patent: 5195097 (1993-03-01), Bogholtz et al.
patent: 5428626 (1995-06-01), Frisch et al.
patent: 5636173 (1997-06-01), Schaefer
patent: 6067255 (2000-05-01), Jung et al.
patent: 6226755 (2001-05-01), Reeves

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