Method for testing jitter tolerance of high speed receivers

Details Method for testing jitter tolerance of high speed receivers Method for testing jitter tolerance of high speed receivers

2006-07-18

2006-07-18

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

72

Reexamination Certificate

active

07080292

ABSTRACT:
A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

REFERENCES:
patent: 5463639 (1995-10-01), Koishi et al.
patent: 5835501 (1998-11-01), Dalmia et al.
patent: 6374388 (2002-04-01), Hinch
patent: 2003/0041294 (2003-02-01), Moll et al.

Affiliated with

Also associated with

Rating

Method for testing jitter tolerance of high speed receivers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for testing jitter tolerance of high speed receivers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing jitter tolerance of high speed receivers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3556035