Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-09-17
2004-06-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S230030, C365S200000, C365S230060
Reexamination Certificate
active
06751140
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for testing integrated semiconductor memory devices, in particular DRAM memories, or the like.
In order to obtain economic yields, in integrated semiconductor memory devices it is necessary to provide repair memory blocks with corresponding repair memory cells or replacement memory cells.
These memory cells of the repair memory blocks are intended to replace defective memory cells that occur. To that end, for each memory module, in particular for each DRAM module or the like, it is necessary to determine a corresponding replacement scheme, redundancy scheme or repair scheme. In order to determine such a replacement scheme, specific tests are carried out on the integrated semiconductor memory device, that is to say in particular on the DRAM memory or the like.
In prior-art methods for testing integrated semiconductor memory devices, in particular DRAM memories, or the like, at least one test is carried out on a memory area of the semiconductor memory device. Test result data for the memory area are generated for each test carried out and/or during each test carried out. For evaluation purposes and/or for further process steps, the test result data of the memory area are buffer-stored externally at least temporarily after a respective test carried out, outside the semiconductor memory device to be tested.
These known methods for testing integrated semiconductor memory devices are disadvantageous to the effect that as the memory size continually increases, that is to say with increasing integration density of the semiconductor memory devices, the bandwidth present for data exchange does not suffice, with regard to the outputting of the test result data, for keeping brief the respective transmission times for the transfer of the result data. Moreover, the respective bandwidth in the transmission channel cannot be increased in a straightforward manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for testing integrated semiconductor memory devices that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that tests integrated semiconductor memory devices, in which the time taken for the transmission of the test result data is particularly short.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for testing integrated semiconductor memory devices, in particular DRAM memories or the like, is characterized in that the test result data of the memory area of the semiconductor memory device are in each case formed, transmitted, and/or stored as a plurality of blockwise test result lists.
Consequently, it is a basic idea of the present invention not to carry out the organization and the transmission of the test result data in a single data block that corresponded precisely to the entire memory area, but rather to carry out the data organization and transmission in a blockwise manner in the form of so-called test result lists. This has the advantage that only the quantity of data representative of a respective block ever arises at a specific point in time and, consequently, the memory and management outlay arises in a temporally apportioned manner. As a result of the method, circuitry necessities such as area-intensive memory circuits or the like can be obviated or reduced. As a result of which, the previous channel bandwidths also remain adequate for data transmission.
Although this procedure is already advantageous when forming a test scheme with only a single test, the procedure according to the invention is appropriate precisely when carrying out a plurality of tests, in particular in a successive manner.
In this case, it is particularly advantageous if each of the tests to be carried out is carried out in a blockwise manner in each case in the memory area. This means that in each case only one area of the overall memory area that is provided and is to be tested is ever tested and that also, as a result, only test result data with regard to this respectively tested block ever arise and have to be managed and transmitted.
Although this is not mandatory, it is preferable for the same block structure to be used as a basis for the blockwise assignment of the test result data to the test result lists and/or the execution of the test.
In this case, it is furthermore preferable for in each case a block structure to be used as a basis that corresponds to that block structure of a blockwise configuration, interconnection, and/or organization of the memory area of the semiconductor memory device in a plurality of memory blocks, in particular in matrix form in each case.
The blockwise test result lists, which may be formed in particular in matrix form, may be formed, transmitted, and/or stored in each case after a specific number or after specific numbers of tests carried out. This is advantageously done after each individual test carried out. This makes it possible, in a particularly advantageous manner, to track the defect evolution of the entire memory area for the individual tests.
The test result lists are configured particularly clearly if they are formed as accumulated blockwise defect lists, in particular as accumulated blockwise defect matrixes or the like, in particular as so-called fail maps or the like.
In this case, the term accumulating or accumulation is to be understood to mean, in particular, the so-called “summation” of defects over a span of tests that are to be executed one after the other. In this case, the accumulated defect list or fail map specifies, after a test Tj which is intended to be the j
th
test in the series of all the tests, which memory cells of the respective block of the memory area have exhibited at least one defect in the previous j tests carried out. If appropriate, the term accumulation can also be understood to the effect that, for each cell of a respective block of the memory area, it is recorded whether and what defect it has exhibited for each of the j tests previously carried out, even though this detailed information will not generally be necessary.
It is particularly preferred that in each case a blockwise accumulated defect list is formed, transmitted and/or stored externally for each individual test carried out and after each test carried out, so that, in particular after carrying out all the tests on all the blocks, accumulating or accumulated defect lists for all the individual tests carried out are present for each of the tested blocks.
The test result list may be accumulated outside the area of the semiconductor memory device, that is to say externally, in particular in an external test device that is provided, if appropriate.
However, it is particularly preferred that the test result lists are accumulated within the area of the semiconductor memory device. In this case, it is then provided that, for each block individually in each case, firstly the respective blockwise accumulated defect list from a previous group of tests carried out or a previously carried out individual test for the respective block is externally transmitted and/or read into the semiconductor memory device, in particular from the external test device that is provided, if appropriate, the test result data or test result lists of the group of tests currently being carried out or of the test currently being carried out for the respective block are accumulated to form a current blockwise accumulated defect list for the respective block, and the respective current blockwise accumulated defect list for the respective block is then transmitted to a point outside the semiconductor memory device and/or stored, in particular in the area of the external test device that is provided, if appropriate.
In order to further shorten the times for transferring the test result lists or test result data, it is provided that the test result lists and, in particular, the accumulated defect lists, for example the defect matrixes or the like, are formed, tra
Schmölz Paul
Spirkl Wolfgang
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
LandOfFree
Method for testing integrated semiconductor memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing integrated semiconductor memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing integrated semiconductor memory devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3336707