Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-06-28
2011-06-28
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C702S120000
Reexamination Certificate
active
07971176
ABSTRACT:
A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
REFERENCES:
patent: 6658616 (2003-12-01), Chang et al.
patent: 6662327 (2003-12-01), Rajski
patent: 6836856 (2004-12-01), Blanton
patent: 7370254 (2008-05-01), Rajski et al.
patent: 7437640 (2008-10-01), Rajski et al.
patent: 7509550 (2009-03-01), Rajski et al.
patent: 2003/0233600 (2003-12-01), Hartman et al.
patent: 2004/0205681 (2004-10-01), Nozuyama
patent: 2006/0005094 (2006-01-01), Nozuyama
patent: 2007/0234169 (2007-10-01), Rajski et al.
patent: 2009/0210764 (2009-08-01), Nozuyama
Cho et al.; “Gate Exhaustive Testing”; in Proceedings of the International Test Conference, Nov. 2005; pp. 182-187.
Ma et al.; “An Experimental Test Chip to Evaluate Test Techniques Experimental Results”; in Proceedings of the International Test Conference, Oct. 1995; pp. 663-672.
Nelson et al.; “Multiple-Detect ATPG Based on Physical Neighborhoods”; in SRC TECHCON, Oct. 2005.
Zachariah et al.; “On Modeling Cross-Talk Faults”; Proc. of Design, Automation and Test in Europe Conference, Mar. 2003; pp. 490-495.
Sengupta et al.; “Defect-Based Test: A Key Enabler for Successful Migration to Structural Test”; Intel Technology Journal Q1'99; http://developer.intel.com/technology/itj/q11999/articles/art—6.htm.
Desineni Rao H.
Kassab Maroun
Motika Franco
Pastel Leah Marie Pfeifer
Chiang Jack
Dimyan Magid Y
International Business Machines - Corporation
LeStrange Michael J.
Schmeiser Olsen & Watts
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