Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-02-22
2001-06-05
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S063000, C365S149000
Reexamination Certificate
active
06243308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a test method for integrated circuit of semiconductor memory device under wafer-level-burn-in, and more particularly the test method will be employed in dynamic random access memory (DRAM) fabrication process.
2. Description of the Prior Art
Generally, semiconductor memory devices are tested by checking whether the intended data can be obtained for input of a particular address signal, thereby distinguishing between good and bad ones. Such as
FIG. 1
, it illustrates wafer-level-burn-in circuitry example of the experimental dynamic random access memory (DRAM). It will be mentioned that as
FIG. 1
, the system according to the prior art is schematically shown to include a plurality of word line, such as WL
1
, WL
2
, WL
3
, WL
4
, WL
5
, . . . to WL
n
a word line driver
101
, a sense amplifier
102
, bit line (BL, BL) respectively. Some small transistors are implemented at each word line edge to simultaneously apply the stress bias to the transfer gates, especially by probing the corresponding test pads. Thus in the past few years, as the above figure shown, the DRAM under wafer-level-burn-in is stressed to word-line and bit-line, respectively. However, unfortunately this cannot be achieved the stress for the effect of cell-to-cell and cell-to-bit-line. Also, the test mode will be executed after all fabrication process completed.
As a matter of fact, in recent years, with advances in miniaturization techniques, the memory cell area has been further reduced. According to the above statement, which in turn has led to an increase in the failure rate attributed to short circuits between adjacent word lines or between adjacent bit lines within the memory array due to processing effects. Therefore, according to the conventional technology, verification of failure has been accomplished by sequentially reading every address location and thus determining the result. However, verification methods have the disadvantage of requiring a test period, which even further increases with the increase of the memory capacity being expanded. Certainly, it is important that spurious indications of defects should not be given. Therefore the testing result contains, in addition to the force cell device and the compared cell device. The cell device identifies digits of the serial checking vectors as to which no determination of correctness should be made.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for testing integrated circuits of semiconductor memory device in wafer-level-burn-in that substantially can verify the disadvantage of requiring at a manufacturing period and which even further increases with the increase of the memory capacity being expanded.
Thus, according to this present invention, an apparatus for testing a dynamic random access memory that has a plurality of electrical cells under the wafer-level-burn-in will be described as follows. Firstly each electrical cell has a transfer gate and a capacitor. Then there are first transistors that respectively are connected with a plurality of odd bit lines for conducting charge stored in the capacitor via the transfer gate. Also, there are second transistors that respectively are connected with a plurality of even bit lines and conducting charge stored in the capacitor via the transfer gate. The first sense amplifiers are connected with the first transistors for amplifying the conducted charge. The second sense amplifiers are connected with the second transistors for amplifying the conducted charge. The first terminals provide a first bit line signal to control first transistors. Finally the second terminals provide a second bit line signal to control the second transistors. Especially, the first bit line signal has a voltage potential opposite the second bit line signal. The other main features of this invention are the following. The first transistors have a plurality of transistors having corresponding gate connected to receive the first bit line signal. The other second transistors includes a plurality of transistors having corresponding gate connected to receive the second bit line signal.
The method for testing a dynamic random access memory having a plurality of electrical cells under the wafer-level-burn-in includes the following steps. Firstly conducting a plurality of odd-numbered lines are carried out for receiving charge stored in each electrical cell of the dynamic random access memory. Then respectively amplifying the received charge from each electrical cell. Again, a plurality of even-numbered bit lines is conducted for receiving charge stored in each electrical cell of the dynamic random access memory. Finally, respectively amplifying the received charge will be achieved from each electrical cell. The odd-numbered bit lines and the even-numbered bit lines are both conducted in alternate periods.
Another embodiment will be described as follows. Firstly, conducting a plurality of even-numbered bit lines are carried out for receiving charge stored in each electrical cell of the dynamic random access memory, followed by respectively amplifying the received charge from each electrical cell. Again, a plurality of odd-numbered bit lines is conducted for receiving charge stored in each electrical cell of the dynamic random access memory. The final step involves respectively amplifying the received charge from each electrical cell. The even-numbered bit lines and the odd-numbered bit lines are both conducted in alternate periods.
REFERENCES:
patent: 5138578 (1992-08-01), Fujii
patent: 5420816 (1995-05-01), Ogihara et al.
patent: 5602772 (1997-02-01), Nakano et al.
patent: 5790465 (1998-08-01), Roh et al.
Mai Son
United Microelectronics Corp.
LandOfFree
Method for testing dynamic random access memory under... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing dynamic random access memory under..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing dynamic random access memory under... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2543577