Method for testing data pins of a parallel communication port

Details Method for testing data pins of a parallel communication port Method for testing data pins of a parallel communication port

1998-12-18

2002-04-09

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

C714S025000, C714S040000, C714S041000, C714S043000, C714S046000

Reexamination Certificate

active

06370594

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a communication port testing module and method thereof which are applied to test the work functions of the pins of the communication ports.
2. Description of Related Art
For extending to the functions, sockets are the basic setting of a computer. For instance, the PCMCIA (Personal Computer and Memory International Association, PCMCIA) communicated port of notebook computer is used to connect with cards such as MPEG card, FAX/Modem card and etc. and to extend the note book computer's function. No matter how these function extending cards need to be connected with the 68 pins of the PCMCIA communication port so that the data can be translated.
For insuring the data of translation process, these pins must be tested and make sure their function is fine. In the prior testing method, Sycard, a testing card will set in the communication port through what the testing process will be operated by the software in the computer to write/read specific data into selected memory division and determined the function of pins by a compare procedure. The test card includes a micro controller, a memory, voltage translator and speaker with 1K Hz. The testing procedure is separated into some functional groups including “Power On/Off”, “Data Pattern”, “Parity” etc. to test the pins.
The prior apply two main testing technique of methods The first is “55AA method”. In this method, the data 55h and AAh will be written and read through the same pins. If the read data was the same with what be written, that prove the accessed pins are fine. The second method is to access any possible data. In other word, if we do to test 8 pins, there will test 256 times and 65536 time for 16 pins.
Being the information for determine whether the pins are open or short, the testing should be done for the each pins. Somehow, for the expensive cost and lousy testing times in the prior art, this invention submits a communication port of testing module and method thereof.
SUMMARY OF THE INVENTION
Therefore, an object of this invention to find out what situation the pins are. A testing module and method thereof are provided to test each pin.
This invention determines the condition, which may be open or short of pins on a testing communication port by comparing the written and read data generation form a write/read testing procedure on a memory unit which is connected to the testing communication port through the pins.
The invention applying a testing controller, a general array logic, a memory unit, and a connection port. Wherein according to a true value table, with the general array logic unit can generates CS signals (Chip Select Signals) by what the common memory and attribute memory in the memory unit can be accessed to resemble the write/read procedures. During the test process, specific data generated by “Walk 0” and “Walk 1” is sent through the pins of a testing communication port in which connected with the testing module. The pins are diagnosed by comparing the written and read data.


REFERENCES:
patent: 5432797 (1995-07-01), Takano
patent: 6058495 (2000-05-01), Lee et al.
patent: 6118711 (2000-09-01), Merritt
patent: 6178532 (2001-01-01), Pierce et al.
patent: 6205096 (2001-03-01), Yeo et al.
patent: 6243307 (2001-06-01), Kawagoe

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