Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-04-12
2002-02-05
Tran, Andrew Q. (Department: 2824)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C714S719000, C714S042000, C714S025000
Reexamination Certificate
active
06345372
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for testing bus connections of electronic circuits, in particular memory components.
Finely structured printed circuit boards, hybrid configurations and, increasingly, multichip modules as well can be used to form highly miniaturized configurations of electronic and electrical components. A multichip module is a configuration in which a plurality of chip modules without cases or housings make contact with one another through the use of a base or carrier. In this case, chip modules are frequently used which represent large-scale-integrated, writable, electronic circuits. Such chip modules are connected at least via an address bus and a data bus to further electronic circuits, for example to processors or to chip modules of the same type. The latter case occurs in particular when the chip modules are memory modules, for example so-called RAMs. Storage elements or storage cells in the interior of a chip module can be addressed through the use of the address bus such that information which is generally binary-coded, that is to say a so-called data item, can be written via the data bus to a cell, and can be read from it. A silicon substrate or a printed circuit board, for example, may be used as the base for the at least one chip module, which in some cases may have no case. Such a construction can be accommodated in a housing or case which, as a rule, has a large number of external electrical connecting contacts which are used for data interchange.
In practice, it has been found that, when constructing finely structured configurations, faults occur in particular when making electrical contacts between a chip module (which, for example, has no case) and a base or the conductors on the base. Faults thus occur, in particular, in the soldered or bonded joints which are required in this case. On the other hand, in order to carry out a connection test, it is generally presupposed that the chip module itself and its base substrate are free of faults, since they have generally been tested separately, in advance. The faults which are possible when a contact-making connection is produced between a chip module and a base may be of different types. A first fault type is referred to as a “stuck-at” fault and relates to a connection like a short-circuit between an address bus line and data bus line. In this case, a so-called “stuck-at 0” or “stuck-at 1” fault relates to a connection from an address bus line or data bus line to ground or to a voltage potential. A second fault type, which is called a “bridging” fault, relates to connections between more than two address bus lines or data bus lines. Finally, a third fault type is referred to as an “open” fault. In this case, an address bus line or data bus line has a discontinuity, such as a disconnection. A so-called “open 0” or “open 1” fault occurs depending on the nature of the line discontinuity, if the potential which occurs on the line is comparable to the level for logic zero or the level for logic one.
Such faults result in a disturbance in the data flow between an affected chip module and an electronic circuit containing this chip module. Faults in lines and contact connections on the base which are part of a data bus or address bus, that is to say the bus connections of a writable and readable integrated electronic circuit, are particularly problematic in this case. With finely structured configurations, such as a multichip module, it is thus necessary to check the connections between the base and the electronic circuit, in particular for the presence of discontinuities.
It is known, for example, for so-called “in circuit” tests to be used to test the connections on the surfaces of printed circuit boards. In this case, special needles or test probes are used to make external contact with selected points on the printed circuit board or with connections with electronic components located on it. This allows signals which occur during operation of the electrical circuit located on a printed circuit board to be tapped off, and to be evaluated in connected, special test apparatuses. However, owing to the small dimensions, this technique cannot be used to test, for example, multichip modules or finely structured printed circuit boards. For this reason, electronic test methods frequently have to be used for such configurations. In this case, selected bit patterns are written to input connections of an electronic circuit, which are present as standard connections and are correspondingly easily accessible. The bit patterns which occur as a reaction to this at further output connections, which are likewise present as standard and are easily accessible, can be evaluated in order to detect, in particular, short-circuits and discontinuities. A test apparatus can be connected easily, for example, if the address and data bus of an electronic circuit is accessible from outside, for example via a plug connector, or if, for example, a memory module which has no case is fitted on a base and there are easily accessible contact points for the lines of the address and data bus on the base surface.
When electronic test methods are used, a fundamental problem which occurs is that a fault on a line of the data bus of the electronic circuit to be tested can indeed be detected by writing and subsequently reading back a pattern of selected test bits. However, using this technique, it is not possible to detect a fault on a line of the associated address bus. In such a case, the test bit pattern is written to a memory cell in the electronic circuit whose address does however not match the respective predetermined address details, owing to the fault which is present. However, when read back, the test bit pattern is once again read from the same memory cell, although this is “incorrect” with respect to the present address details, without any address bus fault appearing to have occurred in this process.
For this reason, special test bit patterns must be used in order to also allow the detection of a fault (caused, in particular by a discontinuity) on the address bus of a writable and readable integrated electronic circuit.
The publication by C. Maxfield, entitled “Testing RAMs and ROMs”; EDN; Feb. 1, 1996, pages 153 to 160, discloses an electronic method for testing connections, for example of memory modules. In this case, a sequence of test bit patterns is written to the lines of the buses of a memory module, and this sequence may be referred to as a “walking-ones sequence” or else a March-0/1 algorithm. In this case, each line of the external address and data buses (which generally have a width of several bits) of a memory module is stimulated once, selectively, with the logic
1
level in a rising or falling sequence, while the other lines of the address or data bus are operated at the logic
0
level. By way of example, for a data bus which has a width of four bits and has the data bits D
3
, D
2
, D
1
, D
0
, this results in the combinations 0,0,0,0; 0,0,0,1; 0,0,1,0; 0,1,0,0 and 1,0,0,0 as test bit patterns.
This method has the disadvantage that a relatively large number of write and read accesses are required in order to detect faults. For example, 64 write accesses and 64 read accesses are normally required for an 8-bit wide address bus and a 1-bit-wide data bus. A reduction to 22 may be possible, but only for the write access. Nevertheless, this still requires 86 memory accesses overall. In contrast, when using the method according to the invention, only 34 memory accesses are required in this example, that is to say 17 write accesses and 17 read accesses, in order to detect and localize possible discontinuities in the address or data bus.
A further electronic test method for the connections of, for example, memory modules is described in the publication by F. d. Jong and A. J. d. L. van Wijngaarden entitled “Memory interconnect test at board level”, published in the 23rd IEEE International Test Conference; 1992; pages 328-337. This test also has the disadvantage that a relat
Dieckmann Andreas
Donderer Markus
Greenberg Laurence A.
Infineon Technologies
Lerner Herbert L.
Stemer Werner H.
Tran Andrew Q.
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