Method for testing, burning-in, and manufacturing wafer scale in

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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3241581, 324755, G01R 100

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active

054402417

ABSTRACT:
A method for probe testing and burning-in integrated circuits formed within dice or chips on a silicon wafer and then optionally either: (1) dicing the wafer into individual chips for shipment or (2) mating the wafer for shipment with a facing substrate having a temperature coefficient of expansion (TCE) matching the TCE of the wafer. Advantageously, the facing substrate is used for both probe and burn-in operations as well as being made a part of the wafer package in option No. 2 above where either the whole silicon wafer or a partial silicon wafer meeting threshold die requirements is to be shipped. In addition, probe and burn-in operations are carried out rapidly at high yields only after all integrated circuit manufacture has been completed.

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