Method for testing a semiconductor memory having a plurality...

Details Method for testing a semiconductor memory having a plurality... Method for testing a semiconductor memory having a plurality...

2006-10-03

2006-10-03

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C365S201000

Reexamination Certificate

active

07117407

ABSTRACT:
A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel memory bank actuation of the memory addresses using an interleaved mode, which is implemented in relation to disjunct subareas of the memory banks, with one another. This shortens the test time required for testing the semiconductor memory.

REFERENCES:
patent: 5862502 (1999-01-01), Giers
patent: 6754116 (2004-06-01), Janik et al.
patent: 6885606 (2005-04-01), Kumazaki et al.
patent: 2002/0083383 (2002-06-01), Lee
patent: 2003/0016578 (2003-01-01), Janik et al.
patent: 2003/0142577 (2003-07-01), Kumazaki et al.

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