Method for testing a semiconductor memory device and a semicondu

Details Method for testing a semiconductor memory device and a semicondu Method for testing a semiconductor memory device and a semicondu

1997-02-04

1998-09-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365194, 365233, G11C 700

Patent

active

058055142

ABSTRACT:
A method and apparatus for performing a specified test on a semiconductor memory device having a clock generating circuit and a control circuit in which the clock generating circuit generates a clock signal in response to an operation request signal and the control circuit generates a reset signal for stopping generation of the clock signal after a predetermined period of time. The control circuit also generates at least one operation control signal for performing a fundamental operation of the memory device in response to the clock signal. The test is performed by inputting a test mode signal to the semiconductor memory device to initiate the specified test, delaying generation of the reset signal for a period of time exceeding the predetermined period of time, carrying out the specified test while the test mode signal is being input, and terminating the specified test by stopping input of the test mode signal. A fundamental operation is performed over a relatively long period of time (a long cycle) in a semiconductor memory device of the type which generates an internal clock signal. Since a failure which appears only in a long cycle operation can be detected, a test for a short circuit between a bit line and a cell plate can be performed.

REFERENCES:
patent: 5181205 (1993-01-01), Kertis
patent: 5519659 (1996-05-01), Tanida et al.
patent: 5625597 (1997-04-01), Hirose
patent: 5640354 (1997-06-01), Jang et al.
patent: 5640509 (1997-06-01), Balmer et al.

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