Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-07-26
2004-01-06
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S523000, C324S763010, C714S735000
Reexamination Certificate
active
06674300
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a method for testing a semiconductor integrated circuit in which a current value of a “static” time power source current is measured with the help of an IC tester and whether or not the semiconductor integrated circuit has a defective portion generated in the manufacturing process is determined based on this result. More particularly, the invention relates to a method and an apparatus for testing a semiconductor integrated circuit that has a complementary metal oxide semiconductor element (CMOS) structure.
BACKGROUND OF THE INVENTION
In a manufacturing process of a semiconductor integrated circuit such as an IC, an LSI, etc. having a CMOS structure, it has conventionally determined whether or not the semiconductor integrated circuit contains a defective portion which occurs in the manufacturing process. By doing so the efficiency of the manufacturing process thereafter can be increased.
Determination of whether or not a defective portion is contained in the semiconductor integrated circuit is generally performed using an IC tester. There are various kinds of sorting methods (testing methods) that use an IC tester. For example, there is a method of measuring the current value of the power source current (hereinafter called “a static-time power source current”) that flows when the IC is out of operation and determining according to this measured current value whether or not a defective portion is contained in the semiconductor integrated circuit.
In this method where connecting an IC tester to this semiconductor integrated circuit of CMOS structure and measuring the power source current of this circuit, the resulting circuit construction becomes the one (hereinafter called “a CMOS transistor”) in which a PMOS transistor and a NMOS transistor are connected in series in the form of a totem pole between the power source and the ground of the tester for measuring the current. Therefore, any one of the PMOS transistor or the NMOS transistor can be made off by fixing each of the respective input terminals of the semiconductor integrated circuit to the power source level or the ground level by means of the tester. It thereby becomes possible to measure the static time power source current. In this case, putting aside a case where the IC has an internal circuit that, even when the IC is kept in the non-operating state, permits a power source current to flow there through, the static-time power source current of the semiconductor integrated circuit usually becomes the sum total of the current values that flow when the CMOS transistors made up on this circuit are being kept “off”. However, this sum total value is very small, and in many cases is on the order of &mgr;A or less.
Generally, in the manufacturing process of a semiconductor, when some drawback occurs in this process, an unnecessary current path is formed in the internal circuit of the semiconductor integrated circuit. In the semiconductor integrated circuit having such an unnecessary current path, even when the CMOS transistor is kept in the non-operating state, the power source current flows into the unnecessary current path that has been formed. The power source current that flows into this unnecessary current path is added to the static-time power source current. For this reason, the current value of the static-time power source current that has been measured when the unnecessary current path has been formed becomes larger than that of the static-time power source current that has been measured when no unnecessary current path has been formed.
Such an unnecessary current path increases the current value of the static-time power source current that flows when the IC is in the non-operating state. Therefore, in addition to increasing the power consumption of the semiconductor integrated circuit, it hinders the normal function and operation thereof even when the semiconductor integrated circuit is in operation. Therefore, the semiconductor integrated circuit that has this unnecessary current path is determined as a defective product.
When performing determination of the defective product of the semiconductor integrated circuit by measurement of the current value of the static-time power source current, ordinarily, it was practiced to fix the internal circuit of the semiconductor integrated circuit to a certain logical state and then perform the measurement once, or it was practiced to change the logical state and perform the measurement a plurality of times. Then, the measured current value is compared with a standard value that is one absolute value, whereby it is determined according to the compared result whether or not the semiconductor integrated circuit was a defective product with an unnecessary current path.
FIG. 11
illustrates a circuit diagram of a conventional static-time power source current measuring circuit with respect to the semiconductor integrated circuit. In
FIG. 11
, one end of a semiconductor integrated circuit
101
to be measured such as an ASIC is grounded, while the other end thereof is connected to a current measuring instrument
102
. A power source
103
is grounded at one end and is connected at the other end to the current measuring instrument
102
. A voltage VDD is thereby applied from the power source
103
to the semiconductor integrated circuit
101
through the current measuring instrument
102
, and a current is thereby supplied to the circuit
101
. On the other hand, a test pattern
105
for setting a logical state is input to the semiconductor integrated circuit
101
. It is thereby possible to set the state of connection in the internal circuit of the semiconductor integrated circuit
101
variously. In the state of connection that has been so set by this test pattern, the current measuring instrument
102
measures the current value IDD. And it is determined according to this measured current value IDD whether or not an unnecessary current path exists within the semiconductor integrated circuit
101
.
FIGS. 12A and 12B
illustrate in block diagram form an example of the internal circuit within the semiconductor integrated circuit
101
and an unnecessary current path therein.
FIGS. 12A and 12B
illustrate an inverter circuit whose PMOS transistor
113
and NMOS transistor
114
are connected in series to each other.
FIG. 12A
illustrates a case where, by the test pattern
105
being applied to their gate, the PMOS transistor
113
has been set to an “off” state and the NMOS transistor
114
has been set to an “on” state.
FIG. 12B
illustrates a case where, by the test pattern
105
being applied to their gate, the PMOS transistor
113
has been set to an “on” state and the NMOS transistor
114
has been set to an “off” state. In
FIG. 12A
, when an unnecessary current path
115
exists between the power source
103
and the drain of the PMOS transistor
114
, it results that an unnecessary current flows between the power source
103
and the ground
104
. At this time, the-current according to the ability of the NMOS transistor
114
flows between the power source
103
and the ground
104
. Similarly, in
FIG. 12B
, when an unnecessary current path
115
exists between the ground
104
and the drain of the NMOS transistor
114
, it results that an unnecessary current flows between the power source
103
and the ground
104
. At this time, the current according to the ability of the PMOS transistor
113
flows between the power source
103
and the ground
104
.
In the semiconductor integrated circuit of CMOS structure, when each of its respective signals including a clock signal changes, i.e., rises or falls, a pass current and charge and discharge currents of the load capacitor temporarily flow by both the PMOS transistor and the NMOS transistor being made “on”. Since this state is temporary, these currents gradually decrease. Then, in a state where each signal has thereafter been fixed, these currents cease to flow. Namely, the logical state of the internal circuit is set as is so by the test pattern that is inp
Aoki Kazuo
Inoshita Chizuru
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Patel Paresh
LandOfFree
Method for testing a semiconductor integrated circuit when a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing a semiconductor integrated circuit when a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing a semiconductor integrated circuit when a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3248683