Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-10-24
1997-06-03
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Testing
365218, 36523006, 3651853, G11C 1140
Patent
active
056361688
ABSTRACT:
A method for testing nonvolatile memory device includes the steps of forming a block including a test row and a first and a second decoding row, by connecting the sources of the memory cells in the test row together to form a common source line, connecting each column of memory cells in the three rows in series, connecting the drains of the memory cells in the second decoding row together to form a common drain line, erasing the memory cells in the first and second decoding rows, successively programming and erasing the memory cells in the test row, and measuring a first drain current flowing through the common drain line with respect to the voltage of the word line of the test row. If the first drain current exhibits a negative threshold voltage, an over-erased memory cell exists in the test row. Thereafter, the total drain current of the memory cell other than the over-erased memory cell and the drain current of the over-erased memory cell can be separately measured for analyzing the tunnel oxide film of the memory cells.
REFERENCES:
patent: 5122985 (1992-06-01), Santin
patent: 5313432 (1994-05-01), Lin et al.
patent: 5371706 (1994-12-01), Frentz et al.
P. Cappelletti et al., "CAST: An Electrical Stress Test to Monitor Single Bit Failures in Flash-EEPROM Structures", The 13th Annual IEEE Nonvolatile Simiconductor Memory Workshop, (1994) pp. 1-3.
NEC Corporation
Nguyen Viet Q.
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