Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-08-29
2004-03-02
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000, C714S720000
Reexamination Certificate
active
06701470
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and in particular to testing memory devices with a tester having a number of data pads which is smaller than that of the memory device being tested.
BACKGROUND OF THE INVENTION
Memory devices are used to store data in computers and electronic products. A typical memory device has a large number of memory cells. Each of the memory cells is capable of holding a data bit in form of a voltage level or an electrical charge. The data bit is written to or read from the memory cell through a write and a read path connected between the memory cell and an input/output pin or a data pad.
During production, the memory device goes through various tests to check for defective cells and read or write path. Typically, to test a memory device, a tester is connected to the memory device. The tester issues a number of test data sequences or commands to the memory device to test the device. The tester collects the test result and checks for errors.
The number of data channels (data pads or pins) committed to testing a memory device is a significant factor in the total expense. Therefore a typical less-expensive tester has a limited resource of a small number of data pads for connecting to only a portion of the data pads of the memory device. Thus, some of the data pads of the memory device are unconnected. Because of the limited resource or reduced data pads from the tester, a memory device is usually designed with an internal test circuit for use during a test using a data compression technique. During the test using data compression technique, a single data bit at a data pad is written and fanned-out to different locations or memory cells by the internal test circuit. Thus, the different memory cells have the same data bits. The same data bits are read in a subsequent read cycle to a match circuit. The match circuit compares the data bits to determine if they all still match. A mismatch indicates a defect in at least one of the memory cells or read/write path. The data compression technique, however, does not test read/write paths of the unconnected data pads of the memory device in one test. Although the same test can be repeated and applied to the unconnected data pads, however, the test would require additional test step. Thus, it would cost more time and is not efficient.
Thus, there is a need for another test method to test memory devices having a different number of pins than the tester.
SUMMARY OF THE INVENTION
The present invention provides a method to test read/write data paths connected between data pads and memory cells of a memory device while a large portion of data pads of the memory device are not connected to the tester.
In one embodiment, a method of testing a memory device with tester is provided. The tester has N number of data pads. The memory device has M number of data pads, where N is smaller than M. The method includes writing data to memory cells of the memory device in a test configuration. Next, the memory device is configured to normal configuration and read and write operations are performed to drive the data from memory cells out to the M data pads and then back into a different set of memory cells. Subsequently, the memory device is configured back to the test configuration and the data is read to the tester to check for error.
REFERENCES:
patent: 5896395 (1999-04-01), Lee
patent: 6324666 (2001-11-01), Nakamoto
Mullarkey Patrick J.
Shore Michael A.
Dildine R. Stephen
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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