Method for testing a memory device

Details Method for testing a memory device Method for testing a memory device

1997-10-08

1999-09-21

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, G11C 2900

Patent

active

059548312

ABSTRACT:
A memory testing method for providing test patterns for a memory device is provided. First, the memory is divided into a plurality of blocks and a test pattern is applied to completely test a first block. Next, the first block is filled with all `1`, and other blocks are filled with all `0`. Then, the first block is walked through the entire memory device to quickly test the memory and the function of the address decoder. The invention provides an efficient method for quickly and completely testing the semiconductor memory as well as detecting and locating all the address decoder faults. A method for selecting an optimal number for dividing a memory device into blocks is also presented to minimize the required test time.

REFERENCES:
patent: H1741 (1998-07-01), Cruts
patent: 4335457 (1982-06-01), Early
patent: 5661730 (1997-08-01), Mitra et al.

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